FPGA PID data type

[StevenA]

I'm using the LV FPGA 8.6 PID function but it has a maximum resolution of fixed point (+-16,5) data.  My analog output module is the 9263 (16 bit). The appropriate data type for that AO module is Fixed Point (+-20,5) data.  With the data type of (+-16,5) you only get about ~14 bits of resolution.  I have an application that requires all the precision I can get.  Has anyone developed an FPGA PID function that is higher resolution?  Specifically one that can do at least fixed point (+-20,5) data?

Steve

[SJL]

I scaled the PID setpoint and process variable from higher-resolution data types to Percent in the (+-16,5) FXP data type.  Likewise, scale the PID output in percent, then convert to  (+-20,5) FXP before you write to the AO module

[bones349]

Im using the FPGA module in LV 8.5.   I noticed a possible bug??  I tried to give the PID(FPGA).vi a Process Variable of FXP (U22,10).

There is nothing listed in the 'help' saying I can't do this, and the FPGA code compiled fine, however... when I wire to it from the Host (with the proper data type) I get an error:

Read/Write Control: XNode is not executable

This node is not executable because an unexpected error occured during code generation.

It'd be nice if the PID (FPGA) vi would throw up an error right away when I wire in the wrong data type.  I'll try to recompile with a small FXP as suggested... but I just wasted alot of time 😞

[JLewis]

Based on your description, the FPGA compile should be fine and the <+,22,10> type should work (although it will be coerced at the node boundary to a <s,16,11>). I recommend doing such coercions explicitly with the To Fixed-Point function as a best practice, but what you have is OK as long as you realize there is quantization (with round-to-nearest-even) happening at the PID input.

The problem you're seeing is specific to the FPGA interface read/write node, and sounds like it is probably a known issue. You might want to search the forums for a workaround and/or repost your question in a new thread as a FPGA interface error.

Jim

[chi_visor]

Hi steve.. I'm facing a similar situation where the AO module that i have, can support (+-20,5) but the output of the FPGA VI supports only(+-16,8). Can you elaborate a little more on scaling and how to do it effectively without loss of precision in the output?

Is there any specific reason for the PID output to be (+-16,8)? Why cant it be of higher resolution?

One more question: I'm running the PID loop at 200us and when i set this sampling time (Ts) in the FPGA PID express vi it auto formats to 0.00s. I'm assuming it sets to 200us internally. Is that correct?

Thanks & regards,

Chirag.