FPGA Compile Worker debug

[Mauritius]

Hello all,

I would like to view the compiled files from the compile worker in vivado.

Does anyone know if possible and how to do it?

Any input would be helpful.

Thanks

[Mauritius]

From this...

https://forums.xilinx.com/t5/Implementation/Where-are-the-Route-Congestion-Metrics/td-p/398427

..it seems like I just need the *.dcp file? 

[NIRebecca]

Hi Mauritius, 

Which compilation file are you looking for? Have you checked C:\NIFPGA\compilation directory?

[Mauritius]

Hi,

Yes, but I do not see the *.dcp file, should I?

But was looking for a some Xilinx file so I could view the mapping/routing utilization of the build FPGA code.

I have some issues with congestion, so one way to see if design has improved could be to have a look at how the FPGA was placed on the FPGA fabric.

[NIRebecca]

Are you using Vivado or ISE to compile?

The dcp would only be included for a Vivado project i.e “C:\NIFPGA\programs\Vivado2015_4\bin”.

In Vivado dcp stands for design check point which is created after each step of the design flow such as synthesis, opt,place, route design. Analogous file type for dcp in ISE are .ngc,.ncd,.ngd. See the table in: Integrating Third-Party IP (FPGA Module)

If you're looking to optimise the compilation you can do this in LabVIEW: Optimizing FPGA Compilation for Area or Speed

Further reading: NI LabVIEW Compiler: Under the Hood

[Mauritius]

I am using a CentOS 6.6 (RedHat) compile worker to compile the FPGA for the cRIO-9039.

It has the Vivado and the ISE installed.

Version is "LabVIEW FPGA Compile Worker 2016"

I do not know if it is the *.dcp file I need? I am not an Xilinx Vivado user - would just like to see how compiler settings / code structure influence the mapping / layout, as that is my issue.

[Mauritius]

Would like to see something like this actually:

https://electronics.stackexchange.com/questions/255171/is-my-fpga-out-of-routing-resources