I’m having a problem setting up a DMA FIFO in my FPGA VI. I’ve created the FIFO in the project, and set it up for Target to host. When I compile my FPGA VI, I get an error stating that “Too many DMA control lines have been requested or some requests are conflicting.” What could this problem be? This is the only DMA FIFO I have in my project. The FPGA properties confirm that I have 3 available on the 9111. Could some requests be conflicting? Why would they be?
Here is my hardware: cRIO w/ 9014 RTC & 9111 FPGA, NI 9862 XNET module, NI 9219 modules.
I’ve tried a number of things including deleting and recreating the FIFO, trying different data types, configurations etc. The only way I can get the FPGA VI to compile is to remove all instances of the DMA FIFO. I’ve taken a shot in the dark on the RT side and made some of the same changes, but all without success (as I expected).
My application is pretty slow, so I could use FP variables if need to, but want to understand what the root of the issue is with DMA. This is the first one of a DAQ project platform that could easily have needs for higher sampling rates and loss intolerance data requirements. Any ideas are appreciated…
