multiple chassis sychronization accuracy problem

[dr-ami]

Hello,

my task is to synchronize 3 pxi-chassis (2xPXI-1044 and 1xPXI-1042) with an pxi-6653 master module and two pxi-6651 slave modules over smb-210 cables. My idea was to propagate the 10MHz OCXO-signal to all three chassis and overwrite the onboard PXI Clocks, this is no poblem but i measured an difference of 17-20ns between the clockout and pfi(0-5) plus additional 17ns between the onboard OCXO and the clockout smb-connector. That means chassis 2 has an offset of 17ns to chassis 1 and chassis 3 34-37nsto chassis 1. This is not bad but also not very good. Is it possible to reduce this time differences or is this the maximum that I can reach with this PXI-665x modules? 

PS: With a additional SMB-cable and a modified signal routing I reduced the time differences to 0-4ns between all three chassis but this is not an perfect solution.

[Marco_Brauner]

Hi,

what I have read is that when you are using a PXI-6653 with Tclk-Software in one PXI-chassis, the skew is about several hundreds of ps down

to 30 ps when you fine-tune the phase of the DACs of your devices. For a multi-chassis configuration, I think it is getting worse a little bit, but not much.

I´m gonna try to find out what the possible trigger-delays are. If you want, check out the TClk-App-Note I´ve added.

http://zone.ni.com/devzone/cda/tut/p/id/3675#toc5

Marco Brauner NIG

[dr-ami]

Thanks for your answer.

I thought TClk requires modules that include an SMC-chip, is that wrong? The R-series modules that placed in my pxi-chassis don't include an SMC-chip also like the PXI-665x modules so I have no idea how I can use TClk. The R-series modules that placed in an pxi-chassis are phase-locked to the pxi-clock so these modules work with little skews. More difficult is to find an reference time with low skew for all chassis. I measured an delay of 17ns from the CLOCKOUT to the PFI connectors (the same OCXO-signal on both connectors), this is my main problem.

dr-ami

[Marco_Brauner]

Hi, Naturally there is a travel-time for the clock-signal from clock-out to your Slaves.

Iif you want to maintain the same latency for all the PXI-Slave-Chassis, the only thing you can do is to match the

cable-length for the Ref-Clock-Signal as perfectly as you can. Furthermore you can adjust how many clocks should occur

until a synchronous trigger is set valid in NI-Sync for compensating for different cable-lengths.

But I think that´s all you can do.

Marco Brauner NIG

[dr-ami]

Thanks for your help. My fear was that I had forget an better possibility. My idea for a better signal routing looks so:

- OCXO 10MHz signal routed to PFI0

- PFI0 is the synchronization clock for all PFI lines (only PFI0 ist possible to do this, not other PFI line)

- synchronization clock send to PFI1-3 (OCXO)

- PFI1 routed to chassis 1 (PXI-6653) CLKIN and overwrites the PXI_CLK10

- PFI2 routed to chassis 2 (PXI-6651) CLKIN and overwrites the PXI_CLK10

- PFI3 routed to chassis 3 (PXI-6651) CLKIN and overwrites the PXI_CLK10

- result: all chassis work now with the same 10MHz base clock (backplane clock), maximum delay I has measured was 4ns beetween the chassis, i think more is not possible with my hardware and also not necessary, the delay of the cables, PFI and CLKIN delay is complete compensated. Perhaps this routing scenario can help anybody else.

MFG dr-ami

[chanu]

Hi can you please post the code used for synchronization of multiple chassis.