Trigger timing with PXI-6653

[jboss]

Hello,

I am attempting to use a PXI-6653 Timing and Synchronization Module to generate a sequence of precisely timed triggers on the different PXI backplane trigger lines. I want to first trigger the PXI-6653 card (probably with a software trigger), and then have it generate a trigger on PXI_STAR_0, then another trigger after precisely 10ms on PXI_STAR_0, then after another 10ms a trigger on PXI_STAR_1. I want this process to repeat every 500ms. All timing must be precise.

Is this possible? If so, how?

Thanks,

John Bosshard

[snowpunter]

I don't think this is possible with a 6653 but you could use a 6608 with three counters.

Counter one would generate a rising edge every 500ms.

Counter two would fire two pulses at 10ms apart when it sees a rising edge on the output of counter one with retrigger set to true, finite generation.

Counter three would fire one pulse 30ms after it sees a rising edge on the output of counter two with retrigger set to true, finite generation, 30ms initial delay (to get the pulse at the right time.)

You'll want to check out the user manual for more info about this but I think it should be possible.

[Justin_E]

Hey jboss,

I believe you can achieve this functionality by using the NI-Sync driver. The latest driver version is 3.0, and can be found here : http://joule.ni.com/nidu/cds/view/p/id/880/lang/en

What you might be able to do is generate a DDS (Direct Digital Synthesis) clock from your 6653 module, divide it, and route that clock into the PXI backplane trigger lines. One example I would take a look at is Generate DDS Clock, Divide and Route.vi, from the NI-Sync examples. This example generates a DDS clock, divides it, and routes the divided clock signal to wherever you specify as the Destination Terminal. You can specify the rate of the clock that you are trying to generate, and use this clock as your trigger signal. You will have to add some additional code to make the clock trigger only however many times you specify. I'd suggest playing around with this example to see if you can get the clock signals routed correctly.

[Jon_M]

You can divide a DDS clock to your heart's content but that's not going to give you two pulses 10ms apart every 500 ms on one line and a another pulse 10 ms after the last pulse on a second line. Not going to happen. This is an ideal counter application.

[Adam_U]

Out of curiosity, what are the pulses going to? And how precisely must they be timed?

Thanks

[jboss]

The pulses will trigger an arbitrary waveform generator (PXI-5412), an analog output card (PXI-6733), and a digitizer (PXI-5122). Timing needs to be accurate at least to microseconds, but preferably even better.

Thanks,

John

[Adam_U]

Thanks.

For resolution in that range, I'd also suggest either a board with counters (this could be M-series or TIO like the 6602 or 6608) or an R-series FPGA board which would allow even more flexibility. This should get you sub-us.