Hello all,
I am using PXIe 5170r 14 bit oscilloscope. I want the module to be used for extracting medical image (demodulator).
I am using the concept of I/Q demodulator receiver in which the received signal has to be multiplied by Sine and cosine values (to be implemented through DDS) and the mixed signal has to pass through Low pass filter. The output of low pass filter is the demodulated signal.
My querry is, the FPGA of PXIe 5170r module work at 125MHz but the ADC at 250MSps, due to this I am getting 2 samples at a time. How to configure DDS to deal with 2 samples at a time? If 2 DDS is used, the first DDS will be configured easily but the second DDS should generate the data which has to be multiplied with the 2nd input data. What should be the POFF value of 2nd DDS so that it will be correctly multiplied with the 2nd input sample data?
If I implement 1 DDS of 250MHz clock frequency and fill the alternate values in FIFO, the code gives an error of unsupported clock.
Please provide hints, solution or any resource to tackle the issue.
Thank You.
Regards.
