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PXI-4461 Filter Delay

Hi,

I have some questions about the Filter Delays associated with the PCI or PXI-4461 card.

I do not have this card, but am interested in it, especially the 24-bit analog output function, to control a test apparatus I have. The problem I face now is that the test apparatus and sensors are sensitive enough to see each bit change in the 16-bit resolution analog control voltage I now use to control the apparatus. I like the sensitivity of my equipment, but do not like seeing the bit changes in the control signal in the resulting data.

I am concerned about how the Filter Delays inherent in the 4461 operation, the roughly 3 milli second delays from instructing the 4461 to output (or input) a signal, and that output signal actually responding (as I understand what the Filter Delay is), will affect the ability of that card being effectively used as an instrument control signal.  I do not want milli second delays interrupting the otherwise smooth control of the test apparatus. I am interested in learning about what triggers a filter delay so it can be avoided if possible.

For example, I might generate an analog output signal to control my test apparatus that consists of several monotonically increasing linear voltage ramps with different slopes, each voltage ramp slope representing a different sliding velocity for the servo mechanism in my test machine to follow.

I could do this by calculating each ramp separately and join them together to make one lengthy voltage ramp / waveform where voltage changes as a function of time vary within the longer waveform. That longer waveform is fed to the DAC to play back at a constant clock rate. Besides the initial start-up of the DAC, I don’t think that there there would be any filtering delays in that example, would there?

However, I do control the machine on the fly so to speak, where changes in the control voltage ramp occurs at arbitrary times without stopping the program, calculations for each DAC update are done right before it’s sent to the DAC. Would each DAC change in this case trigger a filter delay?

Another option to generate a machine control signal is to generate a simple voltage ramp that starts at -10V and ends at +10V that has 16,777,216 values, one for each of the 24-bits. As the program runs, the clock rate is varied which causes the DAC to generate bit changes at different rates, which varies the rate the voltage output changes with time. Will each chang of the clock rate trigger a filter delay?

I realize that there are other ways to increase the resolution of an analog output using 2 or more 12 and/or 16-bit analog outputs, but they too have their limitations. It would be nice to simply have a high resolution analog DAC without the added external hardware and added programming complications associated with the multi DAC output ‘solutions’.  

Any comments regarding the 4461 cards and how they might behave under these scenarios, or suggestions for alternative hardware/software to get a finer DAC output resolution would be appreciated.

thanks,

Brian

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Briank:

The filter delay in an analog output is dependent on the sampling rate that you choose. If the 3-4 ms delay is too much for your application, you can sample at a faster rate. For example, if you sample anywhere between 102.4 - 204..8 kS/s, your delay is 32 samples. This corresponds to a delay of 0.1563 to 0.3125 ms. Do these numbers seem more reasonable for your application?

 

The filter delay happens regardless, it is not triggered. Let's take a filter delay of 1 ms for example. From the time the data is transferred onto the card, there is a 1 ms delay as it propagates through the DAC. There is a constant lag time when using any output channel. 

 

Changing the clock rate during run-time is not supported, the better way to do this would be to sample at the highest rate possible and create an array of data that has multiple samples of the same value to emulate a lower sample rate. This gives you the benefit of having the shortest filter delay time (0.3 ms). 

Nathan Murphy
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Hi Nathan,

 

Thank you for note with some details about the Filter Delay.

 

To be clear; if I were to feed the 4461 an array of values, the filter delay would only be noticed initiating that process, as the time between starting the program and the output of the 4461 changing as the pre-programmed array arrives at the DAC. 

 

If I wanted to have the ability to change the analog output signal as the program was running that was not pre-programmed into that pre-defined array of values, I imagine stopping and re-starting the DAC control loop within a running program using a different previously defined array of values would be my option there? In that case, the delay in updating the DAC output signal would obviously include what ever time LabView takes to stop and restart the control loop and the flow of data to the DAC, plus the Filter Delay which is the 32 samples x the sample rate. Is that correct?

 

thanks for your help,

 

Brian

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You actually wouldn't have to start and stop the control loop to write out new data. You can configure the task to output a specific array at any point - and then yes, you would just have to account for the filter delay. 

Nathan Murphy
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Thank you for that clarification, very helpful.

 

A follow-up question, regarding using a variable clock frequency to vary the rate an output voltage ramp could be changed with respect to time. If I created an array of 16,777,216 points spanning from -10 to 10 volts and fed that to the DAC on the 4461, but used an external clock frequency to control the 4461, and varied that external clock frequency (changed on the fly) to vary the rate the 4461 output voltage varies with respect to time, do you see that as a possiblity? Are there any consequences with respect to the filter delay using an external clock frequency that changes?

 

Related to using an external clock, would the upper limit of an external clock frequency be bound by the 204.4kS/sec spec for the 4461? I assume yes, but would like to verify that.

 

thank you again,

 

Brian

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DSA devices (the 4461 included) use a delta-sigma ADC & DAC, which require a much faster oversample clock to operate. The clocks used in these converters is greater than 13 MHz. Due to this, the use of external clocks to drive the ADCs & DACs is not supported functionality of the cards. You can read a little more about this in the DSA User Manual section on Sample Clock Timebase.

Nathan Murphy
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