FlexRIO maximum input data rate

[VIM18]

Hello.

I'm using a 7966R/6581 FlexRIO system, and want to use the same to perform some IO operations. 

The datasheet (linked here to the relevant page) of the FPGA module says that the maximum data rate is 400 Mb/s for single-ended LVDCI25 operation. I tried searching for what that it is, but I don't seem to be able to find a comprehensive definition for it. I'm planning on sending signals of 3.3 V to the FPGA. I've previously done so with lower speeds (of the order of a few 100 kHz), but I need to push up to about a few MHz now, and I want to ascertain how much error there can be with edge-related timing measurements, if I've to make them.

Please help me understand what exactly LVDCI25 is. I'll be coding using LabVIEW FPGA, are there any adjustments of any sort I might have to make?

Thanks!

[VIM18]

More specifically, I'm trying to perform protocol timing measurements for the I2S protocol using this arrangement. I've done the same for I2C before, and that seemed to work fine. But, considering that I'm working with higher data rates here, I was interested in finding out to what exact level of accuracy I can determine timing parameters for the same. 

Is the edge-placement (and edge-read) resolution simply given by the inverse of the maximum data rate (in this case, 2.5 ns)? Or will I have to consider the timebase accuracy (50 ppm) and peak-to-peak jitter (250 ps) as well? Or, is it something else altogether?

Thanks for the assistance! 

[ARAO]

Hi VIM18,

LVDCI_25 is a Low Voltage Digitally Controlled Impedance, which is an I/O standard.

More info can be found in the Virtex 5 Datasheet, which I have attached (Check page 34).

I'm not exactly sure what I2S is, could you give some description regarding the same, so that I can reply?

Cheers,

Rao

[VIM18]

Hi, Rao! Thanks for your reply!

I'd just made a newer post in the forum, having unfortunately not seen this in time. 

I2S is a communication protocol for communicating audio data between ICs. Data is clocked out with respect to a clock (BCLK, bit clock) to (at most) two different channels defined by another clock (LRCLK, left/right clock or WCLK, word clock).

BCLK is typically of the order of a few MHz, and LRCLK is of the order of a few ten kHz (48 kHz, 44.1 khz, etc.). The setup and hold time values for these cases are of the order of a few nanoseconds, and it is required that we determine these values.

Hence, I was wondering to what resolution these values can be measured, and how this is evaluated. Moreover, in my newer post, I had also enquired as to how exactly this resolution is to be exploited. Is there a better way of doing it that just using an SCTL clocked at the relevant frequency? If not, then what is the ceiling on this frequency that the SCTL can be clocked at?

Thanks!