Mapping to Signals and Initial Conditions in a simulink model

[jhandy]

Hi everyone.  I'm pretty proficient with the old Simulation Interface Toolkit (SIT) and I'm in the process of moving to Veristand.  I have a couple of basic questions that I think I know the answer to, but want to get some verification.

First, when mapping signals, such as the output of an addition block, Is there any way to make them available for mapping other than marking them as test-points?  At the very bottom of this page, it's a little ambiguous but it seems to suggest that if I turn off some optimization option they will all suddenly appear without me needing to mark everything as test points.  The specific text I'm referring to is as follows, "Certain optimizations you enable in Simulink can make a signal unavailable in NI VeriStand. You can disable these options for the entire model to make all signals available for probing, but the memory footprint of the model increases as a result.  Alternatively, you can mark individual signals as test points in Simulink to maintain a reduced memory footprint while keeping the test-point signals available for probing."

My second question is in regards to "initial condition" parameters.  There was an issue in SIT (although National Instruments didn't agree with me at the time that it was an issue), where you could map controls to these parameters, but by the time you were given access to the model, the initialize function had already been called meaning your mappings were pointless.  I can see that I can again map to these parameters in Veristand and I'm wondering if the same issue exists.  I'm not quite to the point where I can start trying to modify these but I am hoping to avoid the days of debugging I wasted on this while learning SIT.

As a follow on the my second question, In SIT, I was able to find the C code (located in nidll_main.c) that was called whenever the "play button" was pressed and add a second call to the initialize function.  This then let me modify initial conditions without recompiling my entire model which in my case, would be unworkable. If this issue does still exist has anyone been able to implement a similar fix?

[Jarrod_S. · Accepted solution]

The optimization you can turn off in Simulink(TM) I believe is called Signal Storage Reuse. To my knowledge you either have to use individual test points on wires, or you have to globally turn off signal storage reuse for your model.

In regards to the second question, the issue still exists in NI VeriStand. It is something that we are aware of that we are looking to address in a future release of NI VeriStand. The workaround you described could possibly work if you do enough digging in the C code. Currently VeriStand loads and then initializes the model at the same time, and code in the initialization could read model parameter values. If you extract this code and move it to the first call to the main Schedule function, you could allow for setting model parameters before the model starts.

[GregWright85]

Hello,

I know this is an old thread, however when researching the same topics in 2019 this is the most relevant item that came up.

I am going through the same process now in Veristand 2019.  Globally turning off Simulink signal storage reuse does not seem to automatically bring every signal into the compiled .dll for Veristand to interpret (unless I am going it wrong).  Is this possible (and this is user error on my part) or are test points the only way?

Secondly, has the initialization issue been fixed?  I want to load default parameter values to take effect at t=0 as well.