split power plane problem

[dbadger]

Hello again friends.  I am trying to create a section inside of my power plane for a different voltage.  I thought I was on a pretty good track, but I am not quite getting there.

First I created a keep out area in the plane that has VCC assigned to it.   Then I created a net group containing only VCC and assigned that group to the keep out area.  So far so good, it is working beatifully to create a square hole in the plane and I can draw other things inside the hole.

Then I created a new copper area inside the square hole (with a some space in between of course) and assigned it to net VCC2 (my second voltage).  I want to have voiding enabled so it will leave a clearance around my signal vias just like the other planes do.

Here is my problem.  If I disable voiding, the whole area fills with copper, but crashes into the vias as I would expect.  If I enable voiding, the whole thing dissapears! 

Does anyone have a clue as to why this is happening?  Is it because it is inside the VCC plane area?

Is there a better way to go about this?

Thanks,

Dave

[dbadger]

I have a couple of new pieces of information.  If I delete the original VCC power plane the problem is still there, so that is not the issue.

If I drag a corner of the copper area outside of the keep out box if begins to fill in the part outside of the keep out area and the voiding works properly where it is filling in.  I still have to turn voiding off to get it to fill inside the keep out area.  It acting like the keep out area is something that it thinks it needs to void around.

Any thoughts?

[_user32]

dbadger ,

Have you considered changing this to a keep-in area?

As with other objects you can double click on the region and launch a popup to change the properties.  You can set the area you've defined as a keep-out or keep-in.  Also you can enable certain layers (by default all layers are on) so as to effect only inner layers (such as gnd/power planes) or outer layers (parts) as needed.

Please try with a keep-in area and please let us know if this helps resolve the situation.

Give me a few days and I can try some variations of keep-out and keep-in and post the Ultiboard files to demonstrate the different performances of using keep-out areas for this purpose. 

Regards,

Patrick Noonan

National Instruments

[dbadger · Accepted solution]

Ok, I apparently was waaaay overthinking on this one.  If I simply just draw the copper area for VCC2 right on top of the power plane, the plane voids around it and everything looks fine.

All of the keep-out stuff wasn't necessary.

Thanks again for the help.