Simulation stopping earlier than TSTOP

[duartejfs]

I am trying to run a simulation of a circuit using a custom current signal. Attached is a picture of the circuit I am trying to simulate and the results of a transient simulation. Even though I have my settings to TSTOP=1s the data stops plotting at about 7ms. I already tried changing the maximum step size, changing initial step size, changing RTOL, but that just speeds up the simulation as it should. Where is this error coming from?

[gabor_csipkes]

I don't know what the PWL time-current pairs are in your design and your screenshot does not show the complete circuit. I created the circuit with only what is visible in the screenshots and for me the simulations runs fine.

One observation though, if in your PWL current cources you have positive current values, those will give negative voltage swings at the opamp outputs. Now, you have your negative supply and positive input both tied to GND. This cuts off any negative voltage swing. If you want asymmetrical supplies you need to raise your positive opamp inputs to an appropriate common mode leve, say VCC/2.

In my experience simulations stop before time if you have convergence issues with your circuit.That will mostly happen due to abruptly changing signals that have 0 rise or fall time, operating point stability issues or badly behaving (too ideal?) circuit models. From your Grapher capture it is not clear if the circuit works as intended up to those 7ms and then stops or if the results are bogus from the beginning in the simulated timeframe. also.