J/K Flip Flop - simulation problem

[as_sk]

There is a some problems with JK flipflop circuit simulation.

Here is an example -

J/K flip-flop circuit 

Expected result is square wave on output.

Actually only constant values are available on output or sometimes simulation is just hangs.

Is it right way to create and simulate flipflop in Multisim Live ?

Many thanks!

[gabor_csipkes · Accepted solution]

It looks like the simulation engine needs a GND reference to perform digital to analog node conversion properly. If you simulate purely digital models in Multisim Live try to create at least one analog voltage in yout circuit which is referenced to 0 (GND). Otherwise the simulator runs into convergence problems and you either see numerical oscillations that are actually not there in a real circuit or no changes at all in the output waveforms.

Also add an analog probe to your schematic. I found this analog probe to be the least intrusive if you associate it with a costant that you later deactivate in the Grapher interface.

I am not sure whether this behavior was intended or not, but it works in a similar manner in Multisim Desktop as well.

For my master-slave JK circuit example see

https://www.multisim.com/content/9uYzZx6CVofGLVd2ab7jTV/jk-flipflop/open/

[as_sk]

Thanks!

Now it seems to be clear for me.

Definitely it should be documented better.

By the way location of additional "analog probe" is also important.

I was able to broke your simulation when moved PR1 from Rn constant to J digital generator.

[gabor_csipkes]

Yes, it looks like it matters.

Interestingly enough, the location of the probe that breaks the simulation is not identical in Multisim Desktop vs. Multisim Live. Multisim Desktop seems to require a probe on a NAND gate output (preferably at one of the Q or Qb flip-flop outputs). Placing a probe on either Sn or Rn breaks the results. Multisim Live gives the correct results in those exact same condition. 

It probably has to do with ideal vs. CMOS or TTL circuit models with different rise and fall times used in the two environments.

[gabor_csipkes]

Yes, I noticed this behavior and it is probably connected to my first answer concerning pure digital node to analog node conversion without a GND reference. The simulator will complain about this. Still, inserting an analog probe in certain points can be a workaround. I changed the analog CK to a digital one and inserted the V probe at the output of the master latch (see capture below). Guess what happens...It does not work for all nodes, but that's how it is.

[as_sk]

Looks like this kind of behavior should be investigated by NI stuff.

An error or warning displaying would be nice, but fixing this issue will be even better.

It's quite hard to explain to students why their design doesn't working as it should be.