12-16-2012 12:34 PM - edited 12-16-2012 12:36 PM
As a part of a larger assignment, I have made this 3 bit counter (see attachments). It should output signals in this order:
000
001
010
011
100
(and this should repeat endlessly.) But it's not working as intended, I am stuck.
I think the problem is that the triggers' outputs cause them to flip back and on, since input comes instantly from their output.
I have trouble finding an element which can cause a few millisecond delay. Any help appreciated.
Solved! Go to Solution.
12-17-2012 10:53 AM
Hi,
Every gate has a delay, the AND gate has a longer delay than the OR gates so your feedback signal can arrive at different rates and it's difficult to pin point which one is causing the problem, even your clock signal is slower than the feedback circuit so control the triggering is difficult. If you were to ground U5A input, you will see the SR outputs are continuously changing.
If I have to create this counter, I would use three cascading flip flops. This way, the clock will control the counter frequency and I don't have to worry about the gate delays.
12-17-2012 11:51 AM
Hi,
In Multisim, there is a component called TRANSPORT_DELAY which you can use to add a delay to your digital signals. This is in the Misc Digital Group and TIL Family. Please take a look at attached example. You can modify the delay times by going in the Properties of this component and under the Value tab, click on Edit model.
Hope this helps.
12-18-2012 01:26 PM
YESSSSS it finally worked. Thanks for replies 🙂
Just in case anyone is interested, see attachments.