synchronize DO-AI with clock

[saf78e]

I am using LV 7.1 and PCI-6024E.

I want to generate a single DO and after a delay to read a corresponding AI...and this to be repeated.

I thought that a clock (1khz) can act as a trigger..the DO to use the rising and AI to use the falling edge..

so the high clock's period will be equal to the delay I want..and the low clock's period will be equal to the time I need for appropriate AI sampling..

I don't have an external clock, so one idea is to have a counter, that produces pulses..and these pulses to be my clock..

In a single vi, I have three different tasks (DO, AI, counter) and the counter's output is the trigger in order to start a single DO-AI sequence. By running the vi continuously, I obtain the repeatative process that I need..

It seems easy, but when I try to implement it, doesn't work..

I am a beginner in the use of DAQ...do i loss sth in the implementation of my process?

Thank you in advance for any suggestions. 

[dcule]

I'm trying to do something similar, though on a PXI chassis. I'm using one of the lines from a 6552 for the trigger, and recording data on a 6030E.

The best approach I've found so far (for what should be a simple task) is this vi: Performing Retriggerable Analog Input Using Two Counters

Cheers.

[thayles]

If you configure a continuous 1KHz counter pulse generation task with the high time equal to your desired delay and set the sample clock source of your analog input task to the falling edge of the counter's output it would seem you would have what you want. The counter's output terminal would serve as the DO as well. You wouldn't need a DO task.

[saf78e]

About the "dcule" suggestions..I will check the "Performing Retriggerable Analog Input Using Two Counters" example
..But is uses the tranditional DAQ functions..and until now I was using the daq as a simulated device..

About the suggestion of "thayles" to eliminate the DO task..the point is that the output of the DO task is not a repeated
pattern but a sequence of 8bits, that changes..and is not either incremental or decremental..but elements of a table..

Another idea is to use the sw delay in a loop..the processes maybe will not be so accurate with the clock but they will have the delay i want..

just that the min delay is 1ms..so the frequency is limited...

I will continue working on this and i will post any progress.

thank you both!