Use of random pulses as sample clock

[Douglasg610]

I am using a S-series PCI 6110 board with a BNC-2090A breakout panel.  Ai0, Ai1, Ai2, Ai3 are analog in, PFI0 is the timing input.  I was able to make the system perform using PFI0 as a trigger under the old DAQ modules, but when I switched to DAQmx modules to use it as a sample clock, the system timed out.  The modules I am using, in order are: DAQmx Create Task, DAQmx Create Channel (AI-Voltage-Basic), DAQmx Timing (Sample Clock), DAQmx Start Task, (Looped), DAQmx Read (Analog 2D DBL NChan NSamp), (End of Loop), DAQmx Stop Task, DAQmx Clear Task. I have set the rate at 1MS/s, the time out at 5, and the number of samples to accumulate as 1000.

     The timing signal is a fast shaper for a nuclear detector, so the pulses occur at random.  I had hoped to accumulate a few thousand samples with this "timing", then process them all at once.  Can the S-series work with a random sample clock, and if so, what must I add?

[ManLongAtNI]

Hello Douglasg610,

Can you verify the function of the signal coming into the PFI line? You mentioned when using the Traditional DAQ VIs (old DAQ modules) you used it as a trigger and when using the DAQmx VIs, you have it as a sample clock. It sounds like you want to acquire a finite number of samples whenever you receive a signal from the PFI line. If that is the case, please reference the following Community Example Finite Retriggerable Analog Input Using Digital Trigger . Due to the 6110s inability to perform a retriggerable analog input, the example uses a counter to generate a retriggerable pulse train as the sample clock.

[Douglasg610]

No, that is not it at all.  I am trying to use the PFi0 line to clock the ADC, so that it samples ONCE for each PFi0 pulse, and it then samples ONCE for each subsequent pulse, and it then stores a great many points in the card memory, and we then Read it all into LabView to process many such points at quickly.

The finite retriggerable sampling is largely inefficient if I A) know exactly when the sample should be taken and B) Only care about the value of the signal at that instant.

[Douglasg610]

To clarify: one sample per pulse, only. 

Also, the 6110 is an S-series board, not E or M.

S:

http://digital.ni.com/manuals.nsf/websearch/735CC93703898ABA862575A000517B07

 E:

http://digital.ni.com/manuals.nsf/websearch/06115536722DAA558625728E007E6BA4

M:

http://digital.ni.com/manuals.nsf/websearch/2025C99AB0614F9E8625748000577B9A

I am not sure if this has any effect on what the S-series boards can or cannot do.

[Brad_K]

Hi Douglasg610,

The ADC used on the PCI-6110 has a three-stage pipeline, so the minimum sample rate listed in the specifications is 1 kS/s. If the time between samples ever exceeds 1 ms, then that sample and the two samples following it will be inaccurate. If you can guarantee that a >1 ms delay between samples never happens, then I think this setup should work for your application.

This KB has an explanation: Why Are the NI 6110 and 6111 Bounded by a Minimum Sampling Rate of 1kS/s?

Also, due to this pipeline, you must provide the PCI-6110 with at least 1003 sample clocks in order to acquire 1000 samples: Why Am I Missing Three Scans From My Buffered Analog Input Using PCI-611x?

Could the number of sample clocks be causing your timeouts? If not, please post some details, such as the error code and description.

Brad

Message Edited by Brad K on 02-08-2010 12:46 PM

[Douglasg610]

The trigger pulse channel to PFi0 is about 933 pulses per second, randomly distributed.  Which means that sometimes the gap is much less than 1.07 ms, and sometimes more.  I set the "Sampling rate" much higher than that, to anticipate the minimum gap between pulses.

[Seth_B.]

Unfortunately, the limit that Brad is mentioning is a hardware limitation, not a software limitation so setting the sampling rate faster in software will not prevent the decay he is referring to.  Samples are only moved out of the ADC's pipeline buffer when there are samples to replace them.  Thus, whenever it takes more than 1 ms for a pulse to arrive, the sample that is returned will have decayed some and will no longer be accurate.  Unless you can be sure that you will get pulses faster than 1ms apart, you will encounter accuracy issues.  Also note that the sample you receive is will be three pulses "behind", due to the 3 sample pipelined ADC.

Regards,