Hello everyone, I use a fpga as a variable timebase clock source to synchronize PCI-6713, the clock signal was routed to PFI_0 in 6713 using a coxial cable. The fpag and 6713 share the same ground, in order to decrease the crosstalk between the clock signal and the analog output, I connect a series resistor(820Ω) in the coxial cable to filter the high frequency so the clock signal RT was increased to 1us, the crosstalk noise was decreased from 30mV to less than 2mV. A software written by complicated C# codes was used to send commands to the card to control the output.
The problem is when I repeat sending same commands to output the same analog output( the analog output time resolution is 2us ), in addition to the normal output, some wrong output that at the end of the program execution the output not returning to 0V occurs! When I checked the buffer size after each running cycle(analog ouput resolution is 2us), the expected sample is 4003, when the output is normal, the generated sample can be 4002、4003、4004; When the ouput not returning to 0V, the generated sample is 4004. If I change the analog output time resolution to 1us、3us、4us、5us、50us, the output is always normal.
What confused me is why the output not returning to 0V sometimes during repeating the same program? What does the clock signal RT affect my output (If I don't connect resistor in the clock wire, the malfunction of output not occurs, but the noise amplitude will be larger)? Why the output is normal if I change the analog output resolution to other values? Why the generated sample difffers after each running cycle? What measurement should I take to get over this problem?
The attachments of figure 1 is a magnified analog output and clock signal, figure 2 is the abnormal output.
Much appreciated if you can help me.
