Analog Input Sample Duration and Signal-to-Noise

[annafourier]

Problem:

Frequently, Fourier Transform Spectroscopy at high resolution is  a photon-starved application. In addition to meeting the sampling requirement one needs to maximize the efficiency by not missing any photons.

We use a PXIe-4492 to sample (continuous scan) interferograms at 10-80 kHz for ca 1 minute per measurement.

Where do we find info on the duration of an individual sample at a given sample rate, or the duration/ period ratio, i.e. the duty cycle ? Can that possibly be increased, for instance by some sample-and-hold stage?

If not, is it possible to synchronize two input channels such that their sampling periods are 180 deg out of phase and each one covers the gaps in the other?

Thanks for any answers

AnnaFourier

[JGoebel]

Hi Anna,

sadly there is no Sample and Hold funtionality on the 4492 Boards.

Of course you can increase your sample-rate to around 200kS/s. If thats still not enough, you can use two channels, and select one to sample on the rising and one to sample on the falling edge of your Samplerate. You can set this option when configuring the Timing, simply have one task use "falling edge" and leave the other one on default values (rising edge).

That way you would get twice as much samples, but you have to make sure that both are synchronized, so consider using a Start-trigger with the sampleclock as trigger-source and then just merge the two waveforms you receive sample by sample.

You could also consider using an external circuit, that holds each photone-value for a certian time, to make sure that every value is acquired, but I guess for a FFT this might influence your measurement result dramatically.

I hope this helps you, if you have any further questions, just let me know!

Best,
Jan Göbel

Staff Applications Engineer

National Instruments

[annafourier]

Hi Jan

thanks much for the answer. The crucial question still is that of the sampling *efficiency* offered by an acquisition board (4492 or a 6361 which is also available, or other). Assuming a 100k samples per sec rate, or 10  microseconds per  'sample': how long is the integration time, over which (photo-)electrons are collected, and how much of those 10 microsecs is lost for the collection process while the system is busy holding, converting and digitizing the collected charge.

If the (total registered electrons/ total arriving electrons) ratio  drops below ~60%  recovering the losses by a sample-and-hold preamp becomes attractive. I take it that none of the suitable DAQ boards features some 'precision switched integrator TIA' front end?

Best regards

AnnaFourier

[Larry_Morgan]

Anna,

I'll provide what information I can to help. Your perception of "sampling efficiency" definitely exists, but is difficult to provide as a hard time specification. At the core of many of our devices, specifically the two you named, are sampling ADCs. As you expect, they spend part of their time sampling inputs, and part of their time converting the sampled inputs to digital codes (albeit with two very different methods). But there is almost always more circuitry involved before the signal gets to the ADC. This circuitry will impose other behaviors that may or may not make a particular device suitable for your needs, and it makes it difficult to provide an easy to comprehend time bound. For instance, if your events are extremely short duration, they might begin and end long before the circuitry of the module you are using can react to them and send them to the ADC.

The sample rates and listed bandwidths of the measurement devices can be somewhat of a clue on how fast the circuitry can respond. 

Diving further into to the specific amount of time the ADC is sampling the signal vs when it is converting the signal it has sampled; this is controlled by the internal clocking of the module you are using. Even if you were able to devise a number for these events, your event would have to be synchronized to the device's internal clocking to guarantee these external events always occurred coincident to the sampling times you expected. Otherwise the clock would be "free running", and have no guarantee of sampling in time. I understand your point about trying to use the ratio of sampling vs converting to understand the likelihood of catching an event, but I'm suspect that might not be an accurate enough way to model your needs to give good guidance.

The 6361 can sample as fast as a 500ns period on a single channel and offers level triggering. It is definitely the better choice for capturing transient events. But you would still want to know how quick these events might be to know if 500ns is fast enough. 

The other option, as you mentioned, is to continuously integrate these events.

I hope this information is helpful to you. 

[Henrik_Volkers]

How about a delta sigma ADC?

Usually no S&H and continuous integration 🙂

I love my NI5922

However, at least it resolves to faster sampling 😉

 And the 5922 fast 😄   but $$  😞

[Larry_Morgan]

Henrik,

The 5922 is indeed a continuous-time delta sigma. However, a large portion of delta-sigma ADCs are switched-capacitor integration. 

[annafourier]

Hello

thanks for all the hints. Yet, sample rate and timing,  details of the ADC or signal shaping by pre-ADC electronics are not critical issues. Indeed, everything is taken care of by the simultaneous (*that* is important)  measurement of a laser reference signal and subsequent Fourier analysis.

But operation in the source-or background noise limit  really requires aggregating as many photo-electrons as possible inside the time interval of one 'data point i.e max. ca 1/2 of the shortest period in the signal, and not miss any signal  between (over-or) samples.

Conclusio: Add an integrating pre-amp (TIA with switchable, purely capacitive feedback (so far found only TI IVC102) to each of the analog input channels, resp. photodiodes.

This should let us determine the elusive, admittedly application-specific, S/N of a DAQ board by simply measuring it. And use if needed.

Best Regards

AnnaFourier