4474 digital filter

[JGS]

I am using a PCI 4474 at maximum sampling speed of 102400 Hz

One of the four analog inputs is TTL signal for time stamps: see attachment with horizontal sample number [#] and vertical input voltage [V].

From the oscillation before the rising edge, it looks as if a digital filter is applied in this board.

With the other signal channels of my application, there is no time margin for such oscillation before the steep rising edge.

Is there an option to disable this feature ? (is my assumption is correct: disable the digital filter?)

I am using LabWindows CVI with DAQmx

I am using Windows 7x64

regards, Jos

[SebSieros]

Hi Jos,

           Just a few questions to clarify the problem.

           Have you confirmed that this is not cause by the signal its self?

           Also what is the setup of your application would it be possible to post any scematics.

           I look forward to hearing from you.

Kind regards

Seb

[Kevin_Price · Accepted solution]

Yes, it's due to internal filtering.

No, there's no option to disable it.  It's inherent in all the NI DSA devices.  See this article for more info.

-Kevin P

[JGS]

Thanks Keven, thanks Seb.

Although I do not like the last anwer (that it cannot be disabled), I will prevent me to do useless experiments.

Jos

[Kevin_Price]

Don't know your whole app, but here's a couple other tidbits that may be of relevance:

1. The filter doesn't change the real-world signal out on the terminal block.  It's just a digital artifact related to the bandwidth-limiting feature (and maybe other reasons too)  of the DSA boards.  If you're sharing that TTL signal with other boards for timing purposes, those boards will get a clean edge without all that pre- and post-transition ringing.

2.  Of course, if you *are* sharing that TTL edge with other boards for timing purposes, you also need to be aware that the digitized signal on the DSA board is *delayed*.  The docs will give details on the size of the delay. 

   Note that if all your data acq is done on the same DSA board, this part of the problem goes away.  All the delays will be equal and would be quite difficult to distinguish from no delay at all.

   If you're using other non-DSA boards, you'll need a scheme to compensate for the delay.

-Kevin P

[JGS]

Hello,

The application is using 2 channels with TTL signal for timing (edge and TTL level detection) and 2 channels with analog signals. The timing and signals are at 2 kHz. I have to measure at  two timestamps (pedestal and hold) in the 500 us window. The analog signals are from electronics with typical 50 us settling time. I need 100 us for noise reduction and timing uncertainties. With a remainider of 100 us and the digitizer running at fastest sample interval of 10 us, I cannot afford +/- 5 samples or more where the digitizer adds a ripple due to steep edge in analog signal.  

[Kevin_Price]

Here's what I think I understand:

- Your math suggests a 250 usec time window of interest.  It sounds to me like one (and maybe both?) of the 2 kHz TTL signals is a 50% duty cycle square wave. 

- You need to allow for 50 usec analog settling time.  Does this directly follow a TTL transition?

- You mention needing an additional 100 usec for noise reduction and timing uncertainties.  I don't follow what this part is about.

- Your remaining time window to analyze is only 100 usec or about 10 samples worth.

- The 5 or so samples of "pre-ringing" before the next transition cuts into your 10 available samples pretty drastically.

- Just guessing, but it generally sounds like your analog signals are a response to that same square wave stimulus, i.e. a series of step responses

What I still wonder:

- why are you using a DSA board to capture such high bandwidth signals?  Do you have any alternatives?

- what characteristics of the analog response are you trying to characterize? 

- would it help to do some curve fitting in the window of interest?  Somewhere between the 50 usec settling point through about 200-250 usec point.

-Kevin P

[JGS]

Hello Kevin,

You understanding is almost correct ie I wrote it almost correctly. One of the 100 us window is for acquiring the average of multiple digitizer samples for noise reduction (ultimo: I have to get statistics far below 1 bit level). The other 100 us window is for getting as-far-as-possible away from steep slopes ie away from ringing effects due to digital filter.

Why this DSA ? We have to cover the dynamic range of 5 decades. For two channels, during one measurement step the signal on channel #1 is 14x the value of channel #2. During the next measurement step, the value of channel #1 is 10^-4 the value of channel #2. I can tune my signals so that channel #2 has a value of 600 mV. This digitizer covers with its 24-bit the required dynamic range without changing gain. And the other specifications seemed sufficient for 2 kHz signal, two data channels and two timing channels all simultaneously sampling.

Regards, Jos