I've been working on a sub-vi for a program and not sure what it might look like for the attached diagram and the following:
1. The digital output module for the sbRIO device resides on the Real-Time target
2. The digital input module for the sbRIO resides on the FPGA target (this is required because there's other functions on the module that require the FPGA)
3. Switch 1 (on the RT target) switches a third party device.
4. If the third party device does not get a reading from its own sensor, it will switch Switch 2
5. The sbRIO will wait time = t seconds then switch Switch 1 again
6a. If the third party device gets a reading from its own sensor, then the sbRIO will switch Switch 3, completing the operation
6b. If the third party device does not get a reading, it will switch Switch 2
7. The sbRIO will wait time = t seconds then switch Switch 1 again
8a. If the third party device gets a reading from its own sensor, then the sbRIO will switch Switch 3, completing the operation
8b. If the third party device does not get a reading, it will switch Switch 4, cancel the operation and send warning signal to Host (aka HMI)
This sub-vi would be integrated into a flat sequence structure on the RT target.
Any suggestions to move the digital imput to the FPGA is highly undesireable because the overall program is mature.
