why is FPGA fifo overflowin​g

[GregFreeman]

Cross post from here. The attachment is on the other thread. Just figured I would possibly get more views or responses on this section of the forum. Please post any responses to the OTHER thread so we don't have two identical threads going. Thanks!

"Please see attached FPGA code. I am taking data for an engine all relative to certain cylinders' TDC. So, if cylinder 1 is at TDC, I grab data, and I continually do so at each tick of a 512 ppr encoder and add it to a FIFO. However, there are multiple cylinders, and each has an offset from cylinder 1. So maybe cylinder 1 is at TDC but cylinder 2 is not there yet so I'm not grabbing data for cylinder 2. When cylinder 2 gets to its TDC I start grabbing its data and adding it to a FIFO. I calculate this by having a counter, which is incremented each time the encoder is ticked. So cylinder 1 obviously has no offset from its self, so it starts taking data right away, then cylinder 2 waits, say, 25 ticks then it starts adding data to its FIFO. Then cylinder 3 does the same, it may be offset by 40 ticks from cylinder 1 so after 40 ticks it starts addding data to its respective FIFO, and so on. Once each cylinders data is available it sets a boolean to true and when all booleans are true I know I have all data which triggers queuing up all the data to send to the RT. If the engine is cycling at 1500 RPM, that means 25 RPS. So every 40 ms it should trigger that all data is there to be queued up to sent to the RT. That is plenty slow enough for the RT to read so the queue doesn't overflow. However, the elements remaining is immediately maxed out and I lose my RT system. It's as if elements are being repeatedly queued up eventhough they shouldn't be. Does anyone see a possible error for this? Attached is my FPGA code.

I know it may be tough to understand everything, I had trouble explaining it, so please ask questions if you are confused and I'll clarify."