while loop in fpga is not executed

[AndyKr]

Hi Pachi,

I further tried to investigate the error and your test.vi for two hours but could not find anything strange. If I run the vi with StepSizeSin <0.5 it is not working for me in LV 2011. Thus I am really surprised that if you run it on your system it gives out the values as you expect. Did you try to run it with values <0.5 in LV 2011? Or do you use a different version of LV? In 2010 it is working for me. And which RT system are you using? My problem LV version is 11.0 and I could not find any updates with the update service.

Thank you for your help. Have a nice weekend.

/Andy

[Pachi]

Hi Andy,

I got hold of a target to simulate your environment, and it does show the strange behaviour you mentioned. All I can say as of now is that this is showing a strange behaviour on FPGA but not on host. I will try to dig into why this is, and if it is expected. Sorry about my lack of presence on forums.

Regards,

[AndyKr]

Hi Pachi,

thank you for your answer and further investigations. For me the most strange thing is that this behavior changed between LV 2010 and 2011. Therefore I think it is not intended and also very strange that it appears just on the FPGA for me.

I am looking forward to your further investigations and results. Maybe there is already a patch or hotfix for this problem? But I could not find anything on the NI webside. 😞

Thanks a lot in advance.

Best regards

Andy

[Pachi]

Hi Andy,

You're right, it is just an FPGA issue. You can run it on host or emulation without issues. I am running a few experiments. Will get back to you soon 🙂

Thanks,

[Pachi]

Andy,

I narrowed down the issue to the feedback node. There is some problem with the feedback node and the configuration you are using, that the developers will look into. A bug report has been filed and we will look into it.

In the meantime, I have a workaround for you. Use a shift register instead of a feedback node. It does the same thing, and you should find better results!

Hope I helped!

Prashanth

[AndyKr]

Hi Prashanth,

thanks a lot for the help. I used your workaround with the shift registers and now my system is finally working again. I was thinking the shift register and the feedback node are the same in the compiled system and that they are just two different ways for a better structure in the block diagram. But obviously they are not. So which one is better to use in an FPGA?

And do you already have some information about the source for the error with the feedback node?

Thanks again, my weekend is saved now.

Andy

[Pachi]

Hi Andy,

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I was thinking the shift register and the feedback node are the same in the compiled system and that they are just two different ways for a better structure in the block diagram. But obviously they are not. So which one is better to use in an FPGA? 

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You're right. A compiler sees both of the the same. There is no change in functionality. The only minor difference is the implementation of the initializer terminal. A feedback node offers you a little flexibility in the sense that you can move the initialiser out, to the loop and in case of nested loops, into any of the loops. You will realise that despite these differences, they work the same way. 

So there is no question of which one is better in an FPGA. The only thing that changes in FPGA paradigm, is that the compiler translates (both FB node and shift register) to an actual shift register in hardware.

However, pay attention to Global Initialization option of the feedback node. If you right click a feedback node, you will see this option in the pop-up menu, and you can configure it to be initialised either at compile/load time or at first call. An initialised shift register, would initialise on each call, and an uninitialised would initialise on first call.

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Thanks again, my weekend is saved now. 

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Its the reason I work 🙂

Glad to see you happier,