what should be architecture to sample 12 channels at FPGA to maximise rate

[junkyard_amoeba]

Hi I'm building a datra logging tool based on FPGA

I'm sampling about 12 channels, on three C-Modules.

also 1 being a digital one to measure RPM.

I want to know what is best way to maximize sampling rate..

currently I sampling each channel in different while loops and then updating their respective variables.

However I saw an example

http://decibel.ni.com/content/docs/DOC-6303

on NI site that sample all channel under one while loop.

when I tried the sampling was real slow.

thanks in advance

mudit

[xseadog]

Wow difficult to grasp functionality of your png.

Suggest you read the tutorial:

http://zone.ni.com/devzone/cda/epd/p/id/6206

Have utilised example to monitor and log 10 channels .

xseadog

[junkyard_amoeba]

thanks I guess this should do the job!