wait for Rising edge trigger

[Cobmetal]

Hi ,

im implemented a state machine , at one of the final states , i need to detect a rising edge of I/O node signal(external signal). The frequency of that signal is much slower than the SCTL clock , i thought to use a while loop inside the SCTL , and stop the condition will be the value of '1' of the signal. im looking for a better solution than a while loop inside the SCTL , hope will get a good solution here .

Thank you in advance.

[OctavioS]

Hello,

I may be helpful to understand where these "external signals" are coming from.

What hardware are you using in conjunction with this project?

[Cobmetal]

Hi , im using a kintex 7 FlexRio 7931.

i have a VHDL code which i instantiated as a clip , on of this clip signals is a clock , which i need to detect a rising/falling edge of it , to start another procedure.

Hope this explanation is better.

Thank you,

[SamuRei]

I have some additional points I'd like to clarify with you: it sounds like your FPGA code is a state machine that uses a SCTL as the while loop of a state machine. You have an input from some user-defined CLIP which takes in an external clock and would like to use the state of this clock signal to determine the logic of whether your state machine moves to the next state or continues to wait. Is this correct so far?

First off, a normal while loop will take an absolute minimum of 3 FPGA clock cycles to execute, so using this inside a SCTL will break timing. If you haven't run into any other problems, you might simply take the clock signal from your CLIP and use that as boolean logic to select a case within your "wait" state. A low or "false" clock should send through an enum that tells the state machine to repeat while a high or "true" input to the case will cause the enum to tell the state machine to move on to the next state. Here's similar logic with a "Select" block in LabVIEW. Not sure if this would meet timing but it's worth trying.

[Cobmetal]

HI , thanks for your reply.

The SCTL clock is much more faster than the external clock , the SCTL is 40Mhz , and the external clock is 100Hz.

I will try to put this logic, and see what happened.

Thank you.