use subVIs on a parent host reference a FPGA VI

[Lasertrap]

Hi all,

I'm trying to create a main Host VI that can act somewhat like a main menu for users. I have another VI that I have added to the main Host VI as a subVI. This subVI includes a reference to a FPGA VI. The main Host VI gives me the following error referring to this subVI: "The subVI is not executable. You must fix all errors in the subVI before this VI can run."

When I open the subVI from its original project folder which includes the FPGA VI it runs normally.

However, now that I have added it to the main Host VI (which is in a new project folder) I don't know how to reference the FPGA VI.

I want to create a main FPGA VI that will include all of my FPGA subVIs (I think this will allow me to execute some FPGA subVIs in parallel, but please correct me if I'm wrong). I'm new to LabVIEW and having a lot of trouble figuring out how to set up the subVIs. I've been messing with the configuration of teh FPGA reference, but still haven't gotten anything to work.

My specific questions are:

In my host subVI how do I reference the correct FPGA subVI?

Where does the FPGA subVI need to be saved? - in the same project folder as the main FPGA VI?

Thank you!

Jen

[nathand]

How do you have your project set up?  Does the original, working VI reside in one project, and your new Host VI is in a different project?  You need to have the FPGA target configured in the project in order to be able to access it in any VI within that project.  You should add the FPGA target to the new project (containing the Host VI), give it the same name as in the working configuration, and add the FPGA VIs under it.  After that it should work, if I've correctly guessed at your configuration.  The actual arrangement of the files and folders on your hard drive isn't important so long as the project references them properly.

[Lasertrap]

Thank you very much! I moved all of the subVIs and FPGA subVIs into the same project. Then I reference the top-level FPGA VI in all of my references. It's working now.

My next question is how to handle errors in the FGPA VIs. I've read that the Interrupt VI and its associated Wait on IRQ and Acknowledge IRQ should go in the top level FPGA and Host VIs. But, how should I handle error outputs from FPGA I/O nodes? In single VIs I had been wiring them to one another and then ending it outside of the While Loop structure with the Simple Error Handler VI.

However, now that I have multiple FPGA subVIs within one top-level FPGA VI, should I include error outputs from the subVIs, wire them together (as a cluster maybe) and then send them to the Error Handler?

[nathand]

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Lasertrap wrote: 

My next question is how to handle errors in the FGPA VIs. I've read that the Interrupt VI and its associated Wait on IRQ and Acknowledge IRQ should go in the top level FPGA and Host VIs. But, how should I handle error outputs from FPGA I/O nodes? In single VIs I had been wiring them to one another and then ending it outside of the While Loop structure with the Simple Error Handler VI.

However, now that I have multiple FPGA subVIs within one top-level FPGA VI, should I include error outputs from the subVIs, wire them together (as a cluster maybe) and then send them to the Error Handler?

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I'm not sure where you read this; there's no problem with using Wait on IRQ and Acknowledge IRQ in subVIs on both the host and FPGA side.

I'm a little puzzled about your program structure.  How are you sending the error from the FPGA to the host (since, of course, you can't run the Simple Error Handler on the FPGA)?  Personally I (almost) never use error wires in FPGA VIs; they use extra space on the FPGA and if an FPGA node returns an error, something sufficiently serious has probably happened (like a hardware failure) that it will require more debugging information than an error code can provide.  If you need the FPGA error information, I'd simply put an error indicator from each one individually on the top-level FPGA front panel, and then let your host read the error information as necessary.