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triggering signal

Hello,
i am doing some acceleration measurement on a gear box. On the shaft there is installed a rotary encoder with 2048 lines. At the casing there is an acceleration sensor.  I want to accquire one acceleration sample each time a falling edge of the rotary encoder occurs.
So the sampling rate will be dependent on the number of revolutions of the gear box.
 
How can i handle this problem?
 
Hardware: PXI-6123
 
Thank you for help!
 
Jens
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Message 1 of 9
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Set up your task to use the falling edge as your clock for acquisition.  Now you will be locked to the speed of the gear box.  Essentially this is a externally clocked continuous data (AI?) acquisition.

 

Paul

Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA
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Message 2 of 9
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Forgot to mention, you will wire in the encoder output to the pfi clock in line you select.

Paul

Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA
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Message 3 of 9
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Thank you very much!

Is PFI0/TRIG1 or PFI1/TRIG2 ther right channel?

Is my vi correct?

Message Edited by Moschdschlotzer on 06-22-2007 08:15 AM

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Message 4 of 9
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Okay,

i think it should work this way! But there is an error message!

Ther german text says:

"Fehler -200019 ist bei DAQmx Read (Analog 2D DBL NChan NSamp).vi:3 aufgetreten
Eine ADC-Konvertierung wurde vor Abschluss der vorherigen Konvertierung gestartet.

Verlängern Sie die Periode zwischen ADC-Konvertierungen. Wenn Sie einen externen Takt verwenden, überprüfen Sie, ob das Signal Rauschen oder Spannungsspitzen enthält."

Here the translation:

"Error - 200019 ...

An ADC-conversion is started before the end of another.

Make the period between ADC-conversions longer. If you use a extern timing signal check if the signal has noise or peaks."

I checked the signal with an oszilloscope. There is some nois and peaks. But how much noise is okay??? Has anyone experience with noisy signals???

regards

Jens

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Message 5 of 9
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to use the external method you need to complete the ADC before the next trigger.  lets say youe encoder is returning triggers at 1Khz you need to complete the ADC in less than .001 seconds.  The other thing is you could have a trigger which is not clean or has too much bounce, where your clock rate will appear much faster than the encoder.

 

Paul

Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA
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Message 6 of 9
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my encoder has 2048 increments and the gear box is driven between 20revs/min till 5000revs/min. So it returns signals between 682Hz and 170666Hz. So i have only time for the ADC between 0,0014 s and 5,8E-6 s!??? So it's a very very short time!!! How fast is the ADC of the NI 6123 card? Do you have an idea to handle this problem?

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Message 7 of 9
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The card should be fast enough it is capable of 500MHz sampling which is plenty fast enough.  You can see if the input rate is correct using the counter on the card, see if the encoder is triggering the counter (should recognize the edges the same as the external clock).  chances are that your signal is not clean enough,  does the encoder put out TTL complient signal?

Paul

Paul Falkenstein
Coleman Technologies Inc.
CLA, CPI, AIA-Vision
Labview 4.0- 2013, RT, Vision, FPGA
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Message 8 of 9
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Hi Paul,

thank you.

The encoder puts out a HTL (Umax > 9V) signal. Not a TTL (Umax=5V) signal.

Do you know wether the PXI-6123 card works also with a HTL signal?

If not i have to build a potenital divider to reduce the potential from 9 to 5 V.

regards

Jens

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Message 9 of 9
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