timed loop frequency

[neil84]

Hi all,

In order to define priority between loops, I should use timed loop rather than while loops, isn't correct?

If I get a ferequency above 1kHz, the Vi don't like.

why am I limited to 1kHz if the processor runs about some MHz?

It's too limited, that means that in order to define priorities the second loop should run below 1kHz. 

thanks

[Norbert_B]

Setting different waiting times in normal while loops is another way to set "priorities" for loops.

Timed loops are available in Windows, but they have been developed for Real Time systems. Since Windows is no Real Time OS, there is a lot of jitter due to OS tasks and parallel running applications. So setting a loop timer to 10ms (100 Hz), the jitter can easily exceed 10ms, even go up to several seconds (indexing of harddrive, start of screensaver,...). So it does not make sense to have a timing <1ms. Windows cannot even guarantee that.....

Running on LabVIEW Real Time, you have a "timing resolution" of 1us, so 1MHz. On FPGA, the most deterministic hardware platform currently available, one has 1 Tick as resolution, which is (without overclocking) 40MHz....

hope this helps,

Norbert 

[neil84]

I tried the timed loop with Labview for ARM module running on the lm3s8962 evaluation board. In this case it sould run roughly like in Labview RT isn't that?

[Norbert_B]

Well, i am not sure if ARM supports the MHz clocksource as well. But if you did not change any configuration, this is expected.

Please read this whitepaper for some information about timing on ARM....

hope this helps,

Norbert