synchronisation single cycle loop start fpga

[Emmanuelle]

I have two timed loops  (single cycle timed loop) running in parallel in FPGA code and I would llike to be sure that they both start at the same time. I tried to use "Synchronizing the start of timed loops.vi" by connecting this vi to the "error" input terminal of both loops. But it doesn't work... labview says the synchronization vi is not executable. Could you help me to synchronize the loops to start on the same clock cycle? thanks

[Thaison_V]

Hi Emmanuelle,

I hope you're doing well.  It sounds like you're trying to use the Synchronize Timed Structure Starts.vi function to start your two single cycle timed loops at the same time.  The Synchronize Timed Structure Starts.vi is meant to run in either the Windows or the Real-Time ETS environment, so that is the reason that LabVIEW gives you the message about the VI not being executable when you have it deployed to your FPGA target.  By default, your single cycle timed loops will be synchronized because they are using the same Master clock from the FPGA.  Typically this is the 40 MHz clock, but if you have your SCTLs running of the same derived clock, they will still be in sync.  Simply by having two timed loops in parallel, running at the same period, and using the same clock, you are already synchronizing the timing of the loops.  Let us know if this helps!

Thaison V
Applications Engineer
National Instruments

[Emmanuelle]

Hi Thaison,

thank you very much for your reply. Since I am using the same derived clock for the two loops it seems I have no problem. The result of running the code also appears to confirm this. What I want to be very sure about is that the initial *start* of execution of the two loops will happen at the same time. Does that automatically happen?

Thanks,

Emmanuelle 

[Thaison_V]

Emmanuelle,

If you want to explicitly ensure that the two loops start at the same time, you can pass dummy wire into the left side of both loops.  This way, both loops don't start until the data is passed to them (dataflow), even if they are not using that data inside of the loop.

Thaison V
Applications Engineer
National Instruments