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simultaneous I/O with DMA FIFO channels on cRio

simultaneous I/O with DMA FIFO channels on cRio

Hy everybody,

I work on a CompactRio 9014, with NI 9263 for analog output and NI 9215 for analog input.

I want to do simultaneous acquisition and generation using DMA channels: one on the first channel for the input and the second on the second channel for the output.

I have already read the example CompactRio Simultaneous AI and AO streaming But, if in this example the Analog input is done by a DMA FIFO, the output is done using the FPGA host interface read/write node (register I/O).

In my case I try to use two DMA channels, one for transfering the input datas and the second to transmit the output datas from the RT vi to the fpga VI.

So I have configure two FIFOs, both of size of about 4000. My sampling rate (for input and output) at the level of the fpga is 20KHz. I want to output blocks of size 2000 and simultaneous read something that is directly linked to my output. The problem, (I suppose)  is that I have to wait on the Invoke Node (wich read block from the Input FIFO) that the reading of the block is completed. In my application, things works well at the beginning but after some seconds the output become instable.

I think the way I program my simultaneous analog I/O is not correct, but I don't see the right way to do that with two DMA channels. I have attached my RT VI and my FPGA VI. (the probleme of I/O is in the case "faulse" in the Room_measurements VI)

I hope somebody can help me.

Thanks in advance for your answers

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Message 1 of 4

Re: simultaneous I/O with DMA FIFO channels on cRio


I now try to separate in two timed loops the input and the output. Each of the loops run at 100ms. The first loop (generation loop) must generate a sinus during 15 seconds(So the loop must run 150 times because dt is 100ms). The second loop (input), must record an input during 30 seconds. I am also not sure if the timeouts parameters of the FIFO read/write are correct.

I think this way (see the jpg) is better. But I still have several problems:
When I launch my VI, it works at the beginning but stops after some seconds (in fact I loose the connexion)
Also, if I stop the output loop before that the input stops, the VI also stops.

I hope somebody can help me

I attache my last_VIs

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Message 2 of 4

Re : simultaneous I/O with DMA FIFO channels on cRio


I'm having the same problem.

I try to do simultaneous acquisition and generation. I have a 9012 compactrio xith 9502 & 9563 for I/O.

I try to use 2 DMA two, but I have a "Glitch", i've try to use the DMA with only 1 element, but it doen't work.

Have your vi ok finaly?

I will see your vis and send mine if they are diffrent.


Thanks in advance for your answer.

Carine Pacheco
Ingenieur Mécatronique et Assurance Qualité
Cedrat Technologies
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Re: Re : simultaneous I/O with DMA FIFO channels on cRio



I am dealing with the CompactRIO 9074 and I have connected the 9870 up to this chassis. I am using the example virtual instrument that was recommended from James. I was able to input all of my Read_FIFO and Write_FIFO with my specific ports, and have modified the ports. When I run the FPGA program, it initializes to step 7, and then exits with the following error message: "Too many DMA channels have been requested or some requested are conflicting. The current target has 3 DMA channels." Does anyone have a fix for this? Thanks.


-Daniel Skrabacz

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