04-17-2013 04:54 PM
hi member
i try to caclute number of clock for this example to caculate the delay for the """for loop with 1000 itration""
after the complition process the vi was excuted on fpga and read the tick count in pc with real time and the number of clock was as shown below 5002 clock
what is this ???
is thier any wrong in my vi
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04-17-2013 05:13 PM - edited 04-17-2013 05:15 PM
What's the problem? It took 5002 clock cycles, which is probably 5 clock cycles per for loop iteration plus 2 cycles of overhead. What did you expect?
If you want one clock cycle per for loop iteration, then you need to use a single-cycle timed loop instead of the for loop.
EDIT: that's assuming that you have the Tick Count VI configured for clock ticks, not milliseconds or microseconds.
04-17-2013 05:29 PM
@nathand wrote:
What's the problem? It took 5002 clock cycles, which is probably 5 clock cycles per for loop iteration plus 2 cycles of overhead. What did you expect?
If you want one clock cycle per for loop iteration, then you need to use a single-cycle timed loop instead of the for loop.
EDIT: that's assuming that you have the Tick Count VI configured for clock ticks, not milliseconds or microseconds.
dear nathand:
i allways wait your answer because your answer always perfect
I think the wrong was from me
I put the single cycle and the number of clock was reduce
thank you
second if I calculate the delay in ms with out put any sigle cycle loop like exmaple above
is it right that the frequency of entire system will be approximate =1/delay
with consider approximation of 12.3 ms will 12!!??
Best regards
04-17-2013 05:51 PM - edited 04-17-2013 05:51 PM
@mangood wrote:
second if I calculate the delay in ms with out put any sigle cycle loop like exmaple above
is it right that the frequency of entire system will be approximate =1/delay
with consider approximation of 12.3 ms will 12!!??
I'm sorry, I don't quite understand your question. Are you asking if the loop rate will be the reciprocal of the delay across the sequence structure? A more accurate way to measure the period of the while loop is to use a single Tick Count wired to a shift register. Subtract the shift register value from the Tick Count value. That will give you the time required for an iteration of the loop. The reciprocal of the loop period is the loop frequency.
04-17-2013 06:13 PM
@nathand wrote:
@mangood wrote:
second if I calculate the delay in ms with out put any sigle cycle loop like example above
is it right that the frequency of entire system will be approximate =1/delay
with consider approximation of 12.3 ms will 12!!??
I'm sorry, I don't quite understand your question. Are you asking if the loop rate will be the reciprocal of the delay across the sequence structure? A more accurate way to measure the period of the while loop is to use a single Tick Count wired to a shift register. Subtract the shift register value from the Tick Count value. That will give you the time required for an iteration of the loop. The reciprocal of the loop period is the loop frequency.
Yes this is what I mean exaltedly
So if make a system (many component add,sub,) and put this system inside the ""while loop""
Then reciprocal of the loop period will be the loop frequency. Or system frequency is this right!!!
-----------------------------------------------
I am sorry for ask stupid question but my work in architecture of systems so these parameter is critical and important to me .
i left my old work on ISE tool from xilinx company because the design of system take very long time so I now moved to labview fpga,its amazing especially in optimization process but the clock Concept here is very weak and totally unclear.
Best regards
04-17-2013 06:22 PM
@mangood wrote:
So if make a system (many component add,sub,) and put this system inside the ""while loop""Then reciprocal of the loop period will be the loop frequency. Or system frequency is this right!!!
-----------------------------------------------
I am sorry for ask stupid question but my work in architecture of systems so these parameter is critical and important to me .
i left my old work on ISE tool from xilinx company because the design of system take very long time so I now moved to labview fpga,its amazing especially in optimization process but the clock Concept here is very weak and totally unclear.
It's a different concept of clock than most FPGA designers use, that's true (I'm slowly learning about this as right now I'm trying to do some software work - C, not LabVIEW - on a processor running inside an Altera FPGA). For a normal programmer it makes sense - it works exactly the way it does on a desktop computer. On a desktop computer you don't need to know how fast the processor is, you just need to know how long it takes your code to execute.
I'm not sure what the distinction is for you between loop frequency and system frequency. There could be other components of the system that run at a different frequency that you don't see but are required by the LabVIEW environment (for data acquisition or communication with the host processor), but your code inside the loop will run at the loop rate that you measure with Tick Count.
04-17-2013 06:34 PM - edited 04-17-2013 06:36 PM
Thank you a lot
all replay with kuds
"""There could be other components of the system that run at a different frequency that you don't see but are required by the LabVIEW environment (for data acquisition or communication with the host processor)""
i will put entire system in single while loop to solve these problem
for last
the delay during move information from fpga to indicator in the front panel of labview during run is consider or not ??
I mean if delay is 1 ms in loop period indicator
is the delay during move this value from FPGA to USB is considered with this 1 ms
I think it did not consider but i need to be sure
Best regards
04-18-2013 03:59 PM
@mangood wrote:
"""There could be other components of the system that run at a different frequency that you don't see but are required by the LabVIEW environment (for data acquisition or communication with the host processor)""
i will put entire system in single while loop to solve these problem
This isn't a problem, and you cannot avoid it. There may be code in the FPGA that does not correspond directly to any part of your block diagram, but is required in order for it to work. Why are you concerned about it? The reason to use LabVIEW is so that you don't have to worry about these details because NI took care of them.
@mangood wrote:
the delay during move information from fpga to indicator in the front panel of labview during run is consider or not ??
I mean if delay is 1 ms in loop period indicator
is the delay during move this value from FPGA to USB is considered with this 1 ms
I think it did not consider but i need to be sure
The time required to update the front panel indicator is not included in the loop period calculation; the indicator updates asynchonously.
04-18-2013 04:22 PM
ok
thank