signal phase offset lag caused through dual DMA FIFOs

[GrantS]

Hi,

    I have been having a problem with feeding two signals from a DAQ read into an fpga by means of dual DMA FIFOs. These two signals are generated from fgen cards and given a certain phase offset between them. A graph placed immediately after the DAQ read in the host VI accurately reflects this offset. However, when these signals are transmitted by DMA FIFO to an fpga, the signal output from the fpga is showing that the phase offset between the signals is not what it should be, what was set at the function generators and read at the DAQ. I'm thinking this has something to do with A) the synchronization between the dual FIFOs at either the host end or the fpga end or B) how the buffered data from DAQ is being read onto the buffers of the FIFOs.

Any help in solving this problem would be greatly appreciated.

Thanks,

Grant

[jareds]

Hi Grant,

It might help to have a little more clarity on what this system looks like.  What FPGA are you using?  What DAQ are you using?  What kind of signal are you outputting from the FPGA and how are you measuring the difference in offset?

If I understand this correctly, you're generating two signals on an FGEN, reading them in on a DAQ and sending those read in signals to an FPGA, which then sends them out along its output.  Is that correct?

Finally, what does the code on your FPGA look like?  Does it have multiple loops?  Are the FIFO Reads in separate loops?  Is there any processing that's going on?

[GrantS]

Jared,

   I am using a 7852R fpga, and a 6115 DAQ. You got the first part right, although I'm not using the fpga analog or digital outputs to observe the signal. Rather, I'm taking the signals that are coming in through the two DMAs and transmitting them out of the fpga serially through one DMA, back onto the host vi.

I'm getting the impression that the phase lag is being introduced by the input DMAs, and I don't believe there is anything wrong with my fpga code, and the problem may lie more in the host. However I'll send along my fpga code along with my host code. I'm just sending along those two files since the llb is pretty large. You should be able to look at the important code even though you won't be able to look at the subvi's

Thanks,

Grant

[GrantS]

Jared, I actually solved the problem just this morning, but thanks to looking into it for me. The problem was being cased by how some of the fpga node wires were being routed. By switching the main branch with the IRQ nodes on it to start the signal out rather than the input DMAs and the secondary branch to start the DMAs, the problem was solved.

[jareds]

Grant,

I'm glad to hear that you were able to get this solved.  Thanks for letting us know!