07-24-2009 11:12 AM
07-24-2009 11:16 AM
07-24-2009 11:59 AM
Sorry, I don't have FPGA, but if the two loops should run in parallel, you need to remove the sequence structure. With the sequence structure in place, the second loop cannot start until the first loop has completed.
Also, shouldn't you toggle the boolean with each iteration? Right now you are only writing FALSE.