question about DMA FIFO and atan2 function

[zyb1003]

 Hello everyone, 

I have been using labview FPGA for sometime, and there are still some problems about DMA FIFO that confuse me. 

Firstly, we know that there is a buffer on the FPGA side. On the host side, there is a larger buffer, too. Now we write FIFO on the FPGA side and read FIFO on host side. This is like you pour water into a tank, and the tank also leaks water. If pouring is faster than leaking, the tank will be full. The same to the buffer I think. So if you place a fifo write on the fpga side in the SCTL, it writes at 100MHZ rate. The writing speed is so fast, so the host buffer is gonna be full at a certain point. so we are sure to lose some points without any way to solve it. Am I right?

Secondly, I use a atan2 function inside SCTL on FPGA side, I also use the DMA FIFO to transfer the value to the host. The problem is when the phase is close to 90, the program has ' error -50440, The transfer didn't complete within timeout period. ' Is it because when arctan(y/x) is close to 90, the y/x might be so large and the fpga cannot calculate it inside SCTL? Any good ways to solve this problem? 

Thank you. 

[MaxJoseph · Accepted solution]

In general, you are right to say that if a buffer fills faster than it empties it will eventually become full. There are three ways to solve this; decrease the write rate, increase the read rate or increase the read size.

Firstly, consider if you really need to record data at 100 MHz. Would data at a rate of 1 kHz be just as informative? Maybe an average and standard deviation or min and max?

Secondly, you can use timed loops to get more deterministic behaviour on your host machine. By putting your FIFO read into a timed loop, you can have more regular reads. You can increase the priority of these loops to ensure they run quickly. Jitter may always be a problem though and you should be ready to handle the buffer full case if data loss matters to you.

Thirdly, a big advantage of DMA FIFO is being able to read an arbitrary number of elements at once. I usually do a 0 element FIFO.Read, which gives me the # elements remaining immediately followed by another FIFO.Read for the remaining # elements. This allows you to use the broadness of the host to take large chunks out of the FIFO in single steps.

By using a combination of these approaches you should be able to avoid buffer overflow and data loss.

As for the ATAN2 issue, I assume it is because the number you are sending is INF. Perhaps you can detect when the INF value and avoid sending it.

[zyb1003]

Thanks for your reply max!

For Arctan2 function, it has two inputs, y and x, I try to detect when y/x is very large, however, in SCTL, it does not let me to use the divide function. Then I try to use the high throughput divide function, however, it has 18 cycles latency. So I still have no idea of how to solve this. 

[MaxJoseph]

Hi,

I am not sure about what is causing the error, which appears to be that the DMA.FIFO is taking too long to write a value. First check the value; send it to the host using a front panel control; does it make sense? Then try to manually write this value into a DMA.FIFO; did it work?

A tip on multiplication and division on FPGA: It takes a long time to do proper divisions on FPGA, so if pipelining and delays are not acceptable you must avoid this! Bear in mind that multiplication and division by powers of 2 (i.e. a = b*2^n) is fast when working with integer types due to the magic of binary! Multiplying an integer by 2, 4, 8 etc or 1/2, 1/4, 1/8 is very quick. There are loads of similar tricks with binary. For this reason I try to stay in integer space on the FPGA rather than using FXP.

If you must be in FXP then consider again pipelining. You can use data valid flags to control output and then make sense of everything on the host later.