need help..please explain to me this part of the programming code...

[JK1]

Hai,

So there is no problem with FPGA code. Now we need to look into RT code.
The below points will be useful to troubleshoot the RT code.

1.  Is the referance to FPGA opened without any error? [while opening reference to  FPGA check if there is any error]
2.  Is there any error while the loop is running?
3. Is RT loop is struck or waiting in some portion of the code
4. Are the indicators in which the values are viewed is of same type as the source datatype in FPGA.  If there is any mismatch there may not be any updation [This has occured to me few times]

[JK1]

Hai,

Just noticed the problem in your code.  The FGPA code must be "Run" from RT.  In your code after opening the FPGA reference you havent run the code so the problem persists.

Look at the picture i have attached to see the run node.  So only the FPGA code runs independantly and in RT code there is no output since you have downloaded the FPGA code but havent run that

I think this should solve the long standing problem Have great week

[xf]

Hi,

thanks for ur suggestions, so I checked error at Open-fpga-vi-reference, viola, indeed there's an err. The error is shown in screenshot. Will you please advise me on how to tackle this?? Thanks.

Oh ya, btw, this VI is modified from an example given by NI, could this be some compatibility problem?

I tried invoke method RUN after open fpgaVI, but problem still exists.I saw this http://forums.ni.com/ni/board/message?board.id=280&message.id=5648&query.id=157646#M5648, so i guess this shouldn't be the problem..

[xf]

The resources for FPGA device has been configured before. http://digital.ni.com/public.nsf/websearch/8203C68AF60F4259862571490077FFF3?OpenDocument

The attachment shows more information about the fpga err.

[xf]

Hi,

The problem of opening the FPGA vi reference is solved.

I've new question:

When I run my host vi and moved the encoder manually, it shows count jumps and ticks (dT) values. However, the PWM Duty Cycle (Ticks) remain zero. I've tested that the last loop in FPGA.vi (both the PID synchronisation loop and the PID closed loop algorithm loop) are running.

Any speculation on where went wrong? Would welcome any speculations, thanks..

[JK1]

Hai,

Good that you arrived at the solution.  Kindly post the solution so that others can get to know the way out when the same problem occur.

Answer to new question:

In the FPGA VI  bottom two loops are linked to each other by two variables.

1. stop pwm boolean

2. PWM duty cycle

3. PID clock boolean

the interlinking may lead to the last loop remain in the while loop without going to calculation loop if 'stop pwm boolean' or pid clock doesnt go TRUE

When the bottom loop is struck in the while loop  then the second loop will not get the pwm ticks as input. I feel that there is some hang up in the last loop i guess

Message Edited by JK1 on 03-24-2009 04:20 AM

[xf]

Hi all..

(1) I'm not sure how the problem of open fpga reference was solved as I did several things. I reselect the bit-file (as I had opened other fpga vi before and probably it had not been closed properly), and it didn't work. It only worked the next day. I read in forum another user also had this problem but got it over miraculously the next day.

(2) Your suggestion made me double check if its is stuck at the left loop (of last loop) and if right loop doesn't get to run. Found out that there is no problem with this. PID clock does go high as can be seen from the indicator, and when this happen, the left loop stops executing and goes to the right calculation. The calculations do proceed, as I added an indicator to test the input current velocity, reference velocity at just before the Discrete PID vi.  Thank you JK for ur suggestions, they helped in set me thinking and testing to verify if my loops are working. Phew, at least now I am sure that they are working fine.

(3) Think the problem is this: the setting of 'Clock Divider', if i set it to one, the output of PID loop is  forever at zero. If I set it to other values (eg100), it can go to 1 sometimes. How do I know which is the appropriate value of clock divider?

Message Edited by xf on 03-26-2009 01:02 AM

[xf]

Hi, I've another new question... it is regarding loopings but I just can't get it right.

What I need to do:

Run the program first and then switch on the power supply to DC motor. The program should disable an FPGA I/O (it is named 'Enable' in FPGA), thus I can then turn on the power supply. If I don't disable the 'Enable' I/O, then when I turn on power, the motor starts turning at that instant.

What I have tried to do:

In host VI, 2 controls are added, 'Run' and 'Okay'. Ideally, I 'Run' the program, and then switch on the power supply, and then finally click 'Okay' and the PWM thinggy should start.

Qns:

1) Is the 'Run'-while loop redundant? there seems to be like many redundant loops?

 2) Under Read/Write node, should 'stop pwm' be removed? Does it make my PWM (in fpga vi) not run after clicking 'Okay'?

3)  Any idea how to loop so that it diasble the 'Enable' I/O but enables it after 'Okay' is set to True?

I have attached both VI. I'm using LV8.0...  Thank You.

[JK1]

I dont have the encoder, pwm vi's hence getting break in the vi.  is it a toolkit? or can you include those vi's in post.

[xf]

Hi JK1,

The sub-vi are not from toolkit, but taken from NI examples. Thank you for taking a look at it.