myRIO FIFO overflow

[ARASH123]

Hi All,

I am using NI myRIO for data acquisition. The sampling frequency is 20 kHz and the number of elements for every loop is 64000. I configured the size of FIFO in FPGA (from properties) and the maximum value that I could give is about 32000 (which makes sense because myRIO has 12 bit and ...). On the other hand, I requested the depth of FIFO size in RT to be equal to 2 times of the total elements that I have (2*64000). I am reading the data with While loop in RT. When I run the program, I miss some of the data and it seems I have more data than the buffer size in FPGA. Is there any solution for this problem? 

When I leave the FIFO size in FPGA (from properties) to be equal to the default one (1023 elements) I still have a similar problem.

I should mention that when I set parameters to acquire lower number of data from FPGA (about 25000) everything works well.

Thanks,

Arash

[MaxJoseph]

There are two buffers for Target-To-Host FIFOs. This took me a while to understand too! Basically, the buffer size you specify in the project window is the buffer on the FIFO. I think this needs to be big enough to handle all the data written into the FIFO between FIFO writes. i.e. probably smaller than you think. The other buffer is in the memory of the host, you access this buffer through property nodes on the host vi. The host side buffer should be large, about twice what you can read per cycle of the host. If you want to fill the buffer prior to reading any of it on the host, make sure it is big enough!

Can I ask; are you recording 64k samples at a rate of 20 kHz, so 20000 x 64000 samples total? Or do I misunderstand?

[ARASH123]

No the total number of data is 64000 per cycle, then the FPGA waits for 100 ms, then the new cycle starts.

The problem is (I think), the RT cannot read the data from FIFO fast enough and increasing the depth of FIFO in host doesn't solve the problem in my case. Am I missing anything? 

[MaxJoseph]

The RT should be able to handle reading 64k samples at 10 Hz. Just to check, are you reading all the elements available in the FIFO each RT cycle? I use a module dedicated to FIFO reading, it has a 0 element FIFO read (to get the number of elements in the buffer) followed by a FIFO read for the number of elements there were in the buffer (if this number is > 0). I then process this simply and package the data for processing by another loop in slow time.

What kind of data processing are you doing with every RT cycle? You might be able to optimise this or shift it to a helper loop. Remember, your RT has immense memory by is very non-deterministic compared to your FPGA, so you might end up using quite different programming styles for the two systems.

[ARASH123]

The sampling frequency is 20 kHz so it takes less than a second for FPGA (I have 4 channels) to collect those data. Yes I am using two FIFO Read in RT exactly like you.

I am not doing that much processing on RT, just reading from FPGA and saving the raw data in a external memory, and sending a few number of data in each cycle for PC for processing (just to monitor how the data look like during the experiment).

[MaxJoseph]

So, you are collecting a total of 64k samples at 12 bits at 20 kHz on each of 4 channels simultaneously. This is quite a lot of data in a short time. Have a look at the transfer rate of the DMA FIFO on your system to check this data rate is possible. Then expand the buffer on the RT side (distinct from the project->FIFO->properties menu) using property nodes on the RT. Provided your FPGA side FIFO buffer isn't being overwhelmed, it should work.

Let me know what your two buffer sizes are.

[Naim_LABVIEW_W]

Hello every one,

 Sorry for may message maybe it's not in the right discussion! but I need help if some one can figure out my problem.  I am new user of Labview, I use to use matlab and dSpace insteed.

I've got labviw 2012 ,I've also installed NIRIO120 for fpga drivers but I am still not able to see my chassis on my labview project (picture).

Could any one please help to resolve the problem and tell if I need to install something else ?

I am not connecting the labview to a real  RIO, I am just doing simulation on my computer.

Many thanks.

Regards,