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multi channel data acquisition from FPGA of the myRIO 1900

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Hi everyone,

 

I would like to ask you about help in my data acquisition and generation program. The main task of this program is to measure 4 channels in adjustable sampling frequency (2 kHz in minimum)  and to generate an analog signal in sampling frequency up to 50 kHz.

I created two loops and everyone is dedicated to the different operation. The first loop is for measurement of the data or writing to the DMA FIFO and the second loop is dedicated for signal generation. I adjust the main parametrs of the both loops in a host vi.

But what is my problem. I compile the program to FPGA of myRIO without any problem and I can run it also but the problem is that sometimes especially when I adjust the lower sampling frequency of the measuring loop the rank of measured channels changes and I see the signal wich is connected from osciloskop to the channel AI0 on the channel AI3. When I stop the program, adjust the higger sampling frequency and run it again it is working well and the signal is on the right channel. Could anybody help me with this problem? I have tried to check all forums which I know but I have not found any article or discussion dedicated to a similar problem.

 

Thanks alot... 🙂 

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Dear Dickynson,

 

Looking at the code you have sent, the way you handle reading information from the DMA was a little confusing to me. To keep the channels consistent, you have to make sure that the DMA  is being read in multiplies of the number of channels all the time, then decimate the output array. I'd try to simplify the channel reading or run the code with probes attached to check how the values change as you switch acquisitin speeds.

 

Regards:

Andrew Valko
National Instruments Hungary
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hi, Andrew,

 

thank you for your response. I have tried the easiest ways of the reading which I have found at the internet and in examples also but it didnt work exactly as I wanted. Recently I have observed this way of the reading and it works without problems but the problem is the sample frequency changing I mean the changing before I run the host VI. I dont understand why the measured channel which was before fo exmaple on the channel 0 is then on the channel 3. I think that could by connected with some adjustment of the FIFO writing on the side of the myRIO but I dont know how to confirm this affirmation. I dont think the problem could be on the side of the host VI but im not sure of course. Do you have some recommendation what I could try to do with this? Thank you

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Andrew,

 

please could you tell me how I could countinuously read or measure the analog signal from 4 channels of myRIO in different way that I do? I practically used the example from the LabView so I dont know how else to do it. Im a begginer in FPGA programming, but i think that this was of reading could work. Unfortunatelly ther is a problem with the changing of the inputs that I dont understand.

Thank you for your answer.

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Solution
Accepted by topic author Petr-Vesely

Andrew,

 

I have just solved the problem. I was thinking about it still and I have got the idea to change the size of the DMA buffer on the side of myRIO. I extended the buffer from 1023 elements to 2047 and it is working well and I can change the sampling rate without problems. 

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Dear Dickynson,

 

is seems that you DMA FIFO was occasionally overflowing then, causing you to lose samples in the process. Thanks for letting me know.

 

Regards:

Andrew Valko
National Instruments Hungary
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Hi! Is the FPGA_stim_seq_seploop.vi dedicated for the FPGA Implementation of Data Acquisition in NI myrio1900? Im looking for a way to implement data acquisition for ecg signals and im hoping i can start from your VI. Thank you!

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