Hey guys,
i found the attached VI showing an moving average filter on a fpga. It is the last part of my lock in amplifier.
I am a bit confused about the meaning of the math part outside the SCTL: 2 x "stages" - 2...is later the delay
Can someone derive me this equation?
And I faced the fact, that when my "stages" value is higher than 1, the output seems sensless. I am also confused, because there is place for 2048 values in the block ram, but when I have the value 2 stages only every second value is stored in the block ram. Is this right?
Greetz
Slev1n
