how to get the sine wave sample of the input and output in the same time?

[Yun_Zhu]

I discovered that the samples were acquired did not in the same time in my vi.Could you tell me how to get the sine wave sample of the input and output in the same time?

Output:9263;

Input:9201

[Anthony_F]

Hello Yun_Zhu,

Your VI looks like you started from an example, and you are on the right track. 

To clarify are you trying to synchronize the input and the output waveforms?  If you you will need to share a time base and a start trigger.  Check out the synchronization examples from LabVIEW

[Yun_Zhu]

Thanks for your reply,Yes,I do want to synchronize the input and the output.I mean The input and the output start at the same time.I have checked synchronization examples. the hardware they used are PXI,DSA and PCI and I couldn't fine the property of syncpulse.src in the example.Maybe,the 9263,9201(I used) don't have this property?If so,what can I synchronize them?Could you give me a example of this type of board?

Thanks

[Anthony_F]

Are these devices part of a compact DAQ system or individual USB devices?

Both will follow the same procedures:

Export the time base from the master device (AI) to a PFI line

Import the time base on the slave device from a PFI line

Start the slave task with a trigger enabled

Start the master task and send the trigger.

If the devices are USB then you will need to physically connect the PFI lines together.

Synchronizing USB Data Acquisition - From One Device to Multiple Systems

[Yun_Zhu]

Thanks for your suggestion.My device is usb-cdaq:9201,9263.Could you give me some example about this device?

Thanks

Yun 

[Anthony_F]

Try this:

Use the analog output module as your "master" - open up the Cont Gen Voltage Wfm-Int Clk.vi example program. 

Set the Physical Channel to be cDAQ1Mod1/ao0

Physically wire ao0 to ai0 from module to module.

Use the analog input module as your slave" - open up the Cont Acq&Graph Voltage-Ext Clk.vi

Set your physical channel to be cDAQ1Mod2/ai0 and set your clock source to be cDAQ1/ao/SampleClock (This will internally route the sample clock from the analog output module to the analog input module)

Start the slave task (this VI).  It will wait for up to 10 seconds (the timeout value) for the sample clock or error.

Start the master task (analog output)