host to DMA compiling but no data is showing

[ghattas.akkad]

hello

i am trying to implement the host to fpga |DMA data transfer i have the virtex 2 labview pci card

the project is compiling and runing

but whenever i select the probe to view data it is always 0  and nothing is going in

how can i debug this and what are the possible errors? i dont not see errors in my design

thank you

[Lennard.C]

Hi ghattas.akkad,

I'm not sure what your code does at the host. Based on what I can see on the code, there might be a few reasons why you are always seeing 0. First and foremost, writting the data before running the FPGA might not be writting the value to the FIFO (I could be wrong). Second, since the sine pattern vi is placed outside the while loop, the value that is written to the FIFO.Write in the while loop is the initial value generated by the sine pattern at the start of the vi. Any values generated by the sine pattern will not be written in the FIFO.Write after the first iteration as while loop will not accept any values other than the value it receives at the first iteration (initial values). 

I could suggest that you can modify your code as following diagram below:

I'm not sure why you would place the sine pattern outside the while loop and write it to the FIFO.Write but place that sine pattern.vi inside the while loop so that as the vi runs, the sine pattern will continuously sends its generated values to the FIFO.Write inside the while loop. 

Hope it helps.

Warmest regards,

Lennard.C

[nathand]

Where are you putting the probe? You cannot probe an FPGA VI during execution on the FPGA target. You may want to set the FPGA VI to execute on your development computer instead (right-click the FPGA target in the project) although I don't know if the CLIP will still work there.

[ghattas.akkad]

ok i updated the design as Lennard.C stated and here is a screenshot of where i am placing the probes

the probes are placed on the wires to see if data is going in or out

thats wrong ?

i do not see any data going out from the fpga fifo side

[nathand]

Is that executing on the FPGA target, or on the development computer? I don't think you can probe wires on a VI running on an FPGA target.

You might want to put some front-panel indicators on the FPGA, for the data and for the timeout. You can see the front panel of a running FPGA VI, although of course the screen won't update as fast as the FPGA is running so you won't see nearly all the data. Are you sure you're feeding the FIFO fast enough to keep it full?

[ghattas.akkad]

the fifo is fed in a while loop from the host vi runing on the pc it should be feeding fast enough i will try to use the fpga vga with indicators to check if the data is really transmitted

[nathand]

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@ghattas.akkad wrote:

the fifo is fed in a while loop from the host vi runing on the pc it should be feeding fast enough i will try to use the fpga vga with indicators to check if the data is really transmitted

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Just out of curiousity, how did you come to the conclusion that "it should be feeding fast enough"? Did you measure the loop rate on the computer? You know that it's consuming 120 million elements per second (120 MHz clock, one element consumed per clock cycle). You are feeding 100 elements per loop cycle on the computer, so that while loop needs to run at 1.2MHz. Do you have any reason to believe that it's running that fast?

On a related note, it is bad practice in LabVIEW (on a computer - this does NOT apply to FPGA) to have a loop that runs as fast as possible with no timing mechanism, because that loop will consume all available processor time and prevent other tasks from running.

[ghattas.akkad]

i can only add a timer in the multiples of ms i cannot change it to double to make loop at 0.000833ms to get the 1.2mhz period

i also tried a timing loop of 1 mhz but still data didnt show on the other side

i thought the while loop will run at a speed taken at least from the cpu which is in ghz and is much higher then the loop the fpga will run at

[ghattas.akkad]

do you have any idea where i can find the files of the following example to check the input variables?

[0utlaw]

Hello ghattas.akkad,

The files associated with that particular example are available on the page that PDF was copied from- a quick search for the name of the document would have located it:

Tutorial: Using DMA FIFO to Develop High-Speed Data Acquisition Applications for Reconfigurable I/O Devices

http://www.ni.com/white-paper/4534/en/

The downloads are listed under the "downloads" section on the right-hand infobox.

Regards,