fpga

[MuratG]

hi there,

i have a crio system with crio-9004, crio-9104 chasis and ni-9201 analog input module. with this system, i want to measure the rms value of input signals and i used the squareroot of sum of squares method between two zero cross'. but i cannot write the code eventually. since the frequency of the signals can change (so the periods) and i cannot find a sample&hold module triggered with an logic signal i cannot manage to write it.

how can i write a vi for the FPGA of 9104 chasis?

thanks

[Thaison_V]

Hi engt,

I hope you're doing well.  It may help to know what version of LabVIEW FPGA and the NI-RIO drivers you are using, but I will assume you are using LV FPGA 8.0 and NI-RIO 2.0 or later.  The overall application should acquire the analog data with the cRIO module and FPGA code, transfer the data to the cRIO Real-Time controller via a DMA channel, process the raw data into the rms value, and then send it back to the Windows host if necessary.

There are shipping examples that show you how to acquire the analog data and send information via the DMA channel, and the RMS value calculation should only require performing the math functions on the Real-Time target.  For the analog input shipping examples, go to Help»Find Examples to launch the NI Example Finder, then Hardware Input and Output»CompactRIO»Basic IO»Analog Input - cRIO.  The DMA example actually does very simple analog input and then sends the data back via the DMA channel, and this can be found under Hardware Input and Output»CompactRIO»FPGA Fundamentals»Basic DMA.

If you need more help with the FPGA/RT Host portion of the code, I would recommend looking at the KnowledgeBase linked here.  Particularly, the LabVIEW 8 FPGA Module Training linked in the KB may be very helpful if you are new to LabVIEW FPGA 8.0.  Lastly, the RMS can probably be calculated using the RMS.vi or RMS Pt by Pt.vi.  Let us know if you run into any trouble, or if there is a specific portion you have questions on.  Have a great day!

Thaison V
Applications Engineer
National Instruments

[MuratG]

Hi Thaison,

Thank you. It has been long since tour post but we were occupied because of a compile server bug (localized Windows) and now we have solved it. We are ready to built our application.

Our application is a power monitor which reads the current and voltage transformer outputs and reads them via ADC (NI9201) and calculates the RMS values, Active and Reactive powers and calculates the harmonics (FFT) if possible. The calculations should be done between two zero crosses of the voltage signals - the utility frequency is 50 Hz and the calculation time is 10 ms). I planned to costruct a FPGA VI that reads the signals and at each zero-cross it updates the RMS and active reactive power values at the system. cRIO is going to work stand alone and there will be no connection to any PC. When I first try the controller I used the zero crossing element under the FPGA Math... >> Control >> Nonlinear... I tried it with a function generator and oscilloscope and worked well except the multiple zero-crosses. When the signal is square then the cRIO senses only one zero-cross but when the signal is sine or triangle then the cRIO shows multiple zero-crosses.

Another handicap is the frequency. The utility frequency is not constant and can vary between 49.5-50.5 Hz (can be 49 - 51 Hz if there is an error at the utility) Since the sampling frequency is constant (500 kHz) then the total number of the samples would change.

I am using LV 8.0, LV FPGA 8.0, NI.RIO 2.0.1. How can I built such a code?

Lastly, there is a Sample&Hold element triggered with time (us to wait for next hold) but I could not find a Sample&Hold element triggered with a logical signal which is time independent.

Thank you again Thaison.

[Thaison_V]

engt,

Good to hear from you again.  Regarding the issue with the Zero Crossing.vi and the square wave signal, is the top or bottom of the squarewave hitting 0 volts exactly?  If so, then your results may be strange.  How are you actually monitoring the number of zero crossings?  The Zero Crossing.vi has a true output for every time a crossing is seen, so to debug and check that it is working correctly with the square wave, you can have a shift register to store a count that increments up 1 everytime a True is received from the "crossing" boolean on the Zero Crossing.vi.

I am not sure what you mean by the number of samples changing.  If you are sampling at 500 kHz, your number of samples should always remain the same from the perspective of your hardware and software.  Could you elaborate on this?

Thaison V
Applications Engineer
National Instruments

[MuratG]

Hi Thaison,

Also nice to hear you too. The problem is not for the square wave, When I connect a sine wave generater to the analog input there occurs multiple zero crosses. For example, when the sine wave crosses from negative to positive then there occurs a -,+ zero-cross and then a +,- z.c. and then again a -,+ zero cross and so on. I count the number of the crosses by an oscilloscope (snapshot).

Zero crossing.vi works fine but this problem is a general handicap while cathcing the zero crosses. To avoid this, in analog circuits there are used monostable circuit to disable the zero cross detecting for a while (maybe 1 ms).

I have built a code for that but cannot make it work properly.

For the sampling rate, of course the rate is constant and does not change. But to measure the RMS of the signal, as I said before, between two zero crosses the RMS calculation is done. (integrate the squares of the samples) So when the utility frequency is 49.7 Hz then the number of total samples becomes (1/49.7) / (1/500000) = 10060 and when the utility frequency is 50.1 then the number of total samples between two zero crosses becomes (1/50.1) / (1/500000) = 9980. The input signal is Utility voltage which is stepped down by a small transformer. OK?

Thanks

[MuratG]

Here the code that I mentioned.

[Thaison_V]

engt,

Thanks for clarifying that a bit.  Is the frequency of the square wave the same as the triangle and sine waves that you are measuring the zero-crossings on?  If so, it's possible that the FPGA is still executing the rest of the calculations and Wait that you have in the bottom While loop, so it may miss the second zero-crossing.  One general suggestions I have--that may or may not be the root of the problem, but it is a suggestion we will want to address anyway--is the way that you are using the Wait functions in your loops.  In the bottom loop, you have it floating in the loop; is this to set the loop time to 10 ms?  You mention that you must complete the calculation within 10 milliseconds, so that's what I assume.  As it is, without having the Wait in some kind of sequence with the rest of the calculations in the loop, we don't know whether the Wait or the calculation will happen first.  If you indeed want the loop timing to be 10 ms, I would use the Loop Timer function.  Take a look at the following LabVIEW FPGA 8 Training slides here.  Slides 4 and 5 in Chapter 4 discuss Loop Timers and show how you can use them with sequence structures to set the loop timing.  So in your case, this would check for a zero-crossing and do the RMS calculation you have implemented every 10 ms.

Regarding your last statement ("Lastly, there is a Sample&Hold element triggered with time (us to wait for next hold) but I could not find a Sample&Hold element triggered with a logical signal which is time independent."), is this what you are trying to implement with the top While loop?  The way you have your VI programmed now, it looks like the top loop is waiting for the DO line to be triggered by the zero-crossing in the bottom loop, then it sets the another DO line high (which is used to trigger the "initialize" input on your integration function), and then it shuts off this trigger DO line again.  One thing I should point out is that to share data between two loops, you typically would use a FIFO or local variable instead of passing it using a DO line.  Your implementation may be necessary if you are using this DO signal externally as well though.  Also, is this Sample & Hold section the functionality that you wish to implement to only calculate the RMS value when a zero crossing happens?  The way you have it implemented now, it will calculate the RMS value no matter if it's a zero-crossing or not, but the top loop is simpling determining whether the value used in the last integration is used or not (this is the purpose of the initialize? input of the Integrator function.  Let me know if you need clarification of anything.  If my descriptions of what you are trying to do don't match up with your intentions, it may be helpful if you give me a step-by-step overview, in words, of what you want your algorithm to do, and I can give suggestions of how to start implementing it in LV FPGA.  Have a great day!

Thaison V
Applications Engineer
National Instruments

[MuratG]

Hi Thaison,

Thanks for your reply. It clarifies some parts a bit.

My aim is to calculate RMS of a voltage input from utility. At the previous jobs it is done by taking the square root of the square integral of the input voltage signal. When I started to program cRIO I planned to calculate the integral between two zero crosses of the signal. When the above value is calculated between two zero crosses then the result gives the RMS x Period/2 (for 10 ms calculation). But since the utility frequency is not constant then the period also should be calculated (or totatl number of the samples between two zero crosses).

As I said before 9201 does not work properly because when I connect it then it sees multiple zero crosses. But when I tried 9215 module then it sees only one zero cross and no other one. Also I tried triangle and square waves. The result is same. Sine and triangle wave causes multiple zero crosses with 9201 but there is only one shot when the input module is 9215. By the way, their frequencies are same.

I have attached the files and they can give an idea about the algorithm of the RMS calculation.

Thanks

[MuratG]

Hi Thaison,

Still you have not reply my message. Is everything OK?

[Rick_K]

The best way to troubleshoot this issue is to verify that the number are actually getting below and above zero. This would ensure that a zero crossing is actually happening. On the FPGA you could use DMA to send the values to the host or just use an indicator.

Also, you could latch comparisons to zero to make sure that the signal actually goes below and above zero. I attached a simple file that will do this. Replace the numeric constant with an I/O node reading the 9215.

Rick Kuhlman
Applications Engineering