hey there,
i am working on the fpga platform and i have to use xilinx vhdl code where i have to recover the clock signal from the encoded data.. so i had used an IP node to configure the vhdl code. but the thing in which i am facing the problem is in giving the clock signal input to the ip node. i am using this ip node in a singl cycle timed loop. since i had never used an ip node before i am not fully aware of the configuration. i wish somebody can help me out asap as i am on a tight schedule.
thank you
vijay raj
