You cannot open references to both VIs at the same time - there can only be one top-level VI loaded on the FPGA at a time. However, you can certainly load one VI onto the FPGA, run it, stop it, then load another VI, as shown in this image:
Here I'm loading one VI to read the module calibration constants at startup, then replacing it with a VI that does the actual I/O and processing loop.
If you have two VIs that need to run on the FPGA at the same time, make one a subVI of the other, merge them into the same VI, or make a new top-level FPGA VI that includes both of them as subVIs. You cannot open a reference to a subVI on the FPGA, only to the top level VI, so you may need to rearrange your front-panel controls.
Message Edited by nathand on 04-13-2007 01:44 PM