fpga disabled code using space on a FPGA

[fengels]

I have a endable/disable diagram for emulation a FIFO during emulation mode. see atached picture.

Does the disabled code use space on an FPGA ( I have not enough space on my 3Mgate FPGA for my program)

I ask this because in some other part of the labview code I had compiling error (in VHDL code) in disabbled laview code.

So it looks like if the disabled code takes space on the FPGA, is this the case?

Frank

[Xavier.Berger]

The code in disable structure doesn't take space on the FPGA, I use it often and it works.

But in your case, i guess you should disable the for loop too. Because you have an empty loop that have an auto-index activated, and since this part is not disabled, it takes space on your FPGA.

Hope this helps,

Xavier

[fengels]

Thanks,

by the way the  2 for loops is the same loop, I only made a picture with the enable and disable.

Frank