Hello there!
I've made a very easy Labview FPGA VI. And sometimes the compiling process finishes without any problem.
But if I use a comparison like "bigger than" ther comes only the following message.
Release 7.1.03i - Xilinx CORE Generator IP_H.16
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Regenerating IP...
the output directory. Output products for this core may be overwritten.
Generating Implementation files.
Generating the VHDL instantiation template.
Generating VHDL structural model.
Finished Regenerating.
Successfully generated core_prim_gt_0003gtsigned16.
After that the compile server shows the message "idle.." without any error.
I am a beginner in programming with labview. How do I compile a VI? Perhaps I'm doing sth. wrong.
My Labview version is 8.0.1 . I recently updated because I thougth that could help.
Thx for every help!