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fpga compilation xilinx error 'Process "Map" failed' - 'unroutable situation'

When I try to compile a Labview fpga project on our new system, it fails with the following error summary (the full Xilinx log is attached):

LabVIEW FPGA:  The compilation failed due to a xilinx error.

Details:
ERROR:LIT:536 - IBUF symbol "aUserGpio<1>_IBUF" (output
   signal=aUserGpio<1>_IBUF) has the attribute IOBDELAY set to value NONE and it
   is driving an IODELAY. If the IOBDELAY attribute is on the driving PAD, it
   has precedence over the IBUF one.  Either the constraint or the design need
   modification to prevent an unroutable situation.
Errors found during logical drc. 
Design Summary
--------------
Number of errors   :   1
Number of warnings : 349
Process "Map" failed


Start Time: 10:31:49 AM
End Time: 10:55:32 AM
Total Time: 00:23:43

Hardware:

  • NI PXIe-1071 Chassis
  • NI PXIe-8108 Embedded controller
  • NI PXIe-7965R FPGA FlexRIO FPGA module
  • NI 5761 250 MS/s 14 bit Analog input digitizer

Installed software:

  • Labview 2011 version 11.0
  • Labview FPGA module 11.0.0
  • FPGA compilation tools (Xilinx12_4)
  • NI FlexRIO Adapter Module Support 2.2.0
  • NI-RIO 4.0 (FlexRIO 2.1.0)
  • Xilinx DRAM compilation bug fix patch from NI article id 5E4FNCDP
  • Xilinx clock bug fix patch from NI article id 5GFAB7DP
    replaces c:\NIFPGA\programs\Xilinx11_5\ISE\xilinx\lib\nt\libPlXil_Clocks.dll; The installed version is c:\NIFPGA\programs\Xilinx12_4-> Manually copied the dll to the installed version

The Project uses the 5761 low speed clip and a DRAM FIFO.

I tried to compile it before installing any patch, after installing the DRAM patch, and after installing both patches and always got a Xilinx error after ~10 minutes compile time. The error summary shown above and the attached Xilinx log are from compiling with both patches installed.

 

It compiled correctly on our older system:

Hardware:

  • NI PXIe-1082 Chassis
  • NI PXIe-8133 Embedded controller
  • NI PXIe-7965R FPGA FlexRIO FPGA module
  • NI 5761 250 MS/s 14 bit Analog input digitizer

Installed software:

  • Labview2011version10.0.0
  • LabviewFPGAmodule10.0.0
  • FPGAcompilationtools (Xilinx11_5)
  • NIFlexRIOAdapterModuleSupport2.1.0
  • NI-RIO3.5.1 (FlexRIO1.5.0)
  • XilinxDRAMcompilationbugfixpatchfromNIarticleid5E4FNCDP

Any help / suggestions greatly appreciated,

Fabrizio

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Message 1 of 5
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Hi Fabrizio,

 

Would it be possible to post your code so that we can reproduce and investigate this failure?

 

 

Regards,

Kareem W.
National Instruments
Web Product Manager
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Message 2 of 5
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Hi Fabrizio,

 

We have a similar issue with 2012 -  it was OK with 2011 - We get the same error message from the xilinx layer.

Did the issue ever get resolved? If so, what was the resolution?

 

Thanks in advance for any help...

 

Rgds, T

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Hi Torpedotown, 

Can you tell me what version of FlexRIO Adapter Module Support you are using? 

The 5761 Low Speed CLIP has a constraint that doesn't work properly with some versions of the compilation tools.  In order to solve this you should be able to upgrade to our latest version of FAM support, or go change the constraint manually.  

 

For the latest version of FAM support, go to http://ni.com/info and enter code "famsoftware"

 

If you've modified constraint files before and feel comfortable doing it yourself, let me know and I can provide you with the details on how to do that. 

 

Thanks!

National Instruments
FlexRIO & R-Series Product Support Engineer
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Message 4 of 5
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Hi Dave,

Thanks for the response.

The FAM software update has fixed the problem!

Rgds, T

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