filter on FPGA vi

[chaude brews]

Hi,

I'm trying to make a simple FPGA I/O vi for a closed loop control system, and I'm wondering if anyone has tips for reducing signal magnitude at ~300Hz with minimal phase shifts. I've tried the butterworth and notch filters and can't seem to improve my result with these as their associated shifts just make my problem worse. Is there anyway to use a window and output only about 1-280Hz?

Thanks

[srm@viewpointusa.com]

what is the response of the system you are trying to control?  what is your acquisition rate? what order filter did you use? what cutoff frequency did you try?

[chaude brews]

I'm controlling an acceleration signal for AVC. My sample rate is 50KS/s, and I've tried 4th order LP Butterworth filters with multiple cuttoff frequencies from 150-300 Hz. I've also tried using countless arrangements of notch filters, but the system is very sensitive to any phase effects.

[srm@viewpointusa.com]

what do you think the response of the system is?

controlling velocity would be more typical.  achieving acceleration by controlling velocity ramp.

why acceleration?

[chaude brews]

I'm using acceleration because the amp that powers my accelerometer only outputs the veloctiy signal in a very narrow bandwidth (~1-110Hz), whereas acceleration responds in  a broader range from ~1-450Hz. I've been staying away from integrating the signal to stay away from noise and lag....plus I can find a way to integrate the signal cleanly on the FPGA.

[srm@viewpointusa.com]

what is the desired frequency response?  what is your control system capable of?