error code 6

[Emmanuelle]

hello,

I have the error code 6 during my compilation.

ERROR:HDLParsers:3010 - "C:/NIFPGA80/srvrTmp/LOCALH~1/TEST2_~2/buildarray_001c.vhd" Line 25. Entity buildarray_001c does not exist.
ERROR:HDLParsers:3312 - "C:/NIFPGA80/srvrTmp/LOCALH~1/TEST2_~2/buildarray_001c.vhd" Line 28. Undefined symbol 'enable_out'.
ERROR:HDLParsers:3312 - "C:/NIFPGA80/srvrTmp/LOCALH~1/TEST2_~2/buildarray_001c.vhd" Line 28. Undefined symbol 'enable_in'.
ERROR:HDLParsers:1209 - "C:/NIFPGA80/srvrTmp/LOCALH~1/TEST2_~2/buildarray_001c.vhd" Line 28. enable_in: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/NIFPGA80/srvrTmp/LOCALH~1/TEST2_~2/buildarray_001c.vhd" Line 29. Undefined symbol 'array_out'.
ERROR:HDLParsers:1209 - "C:/NIFPGA80/srvrTmp/LOCALH~1/TEST2_~2/buildarray_001c.vhd" Line 29. array_out: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/NIFPGA80/srvrTmp/LOCALH~1/TEST2_~2/buildarray_001c.vhd" Line 29. Undefined symbol 'ie1'.
ERROR:HDLParsers:1209 - "C:/NIFPGA80/srvrTmp/LOCALH~1/TEST2_~2/buildarray_001c.vhd" Line 29. ie1: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "C:/NIFPGA80/srvrTmp/LOCALH~1/TEST2_~2/buildarray_001c.vhd" Line 30. Undefined symbol 'ie2'.
ERROR:HDLParsers:1209 - "C:/NIFPGA80/srvrTmp/LOCALH~1/TEST2_~2/buildarray_001c.vhd" Line 30. ie2: Undefined symbol (last report in this block)
-->

Total memory usage is 98680 kilobytes

Number of errors   :   11 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...

What does it mean? what must I do to solve the problem?

Thanks,

emmanuelle

[Thaison_V]

Hi Emmanuelle,

I hope you're doing well.  Are you trying to use DMA output?  Also, is it just this particular VI that won't compile for you, or can you even compile a simple FPGA VI?  If it is just this particular VI, what are some differences between it and the other VIs that can't compile?  We may be able to try to compile the VI on our end to test it out if you are seeing this behavior only in this one VI and you are not doing DMA as discussed in the article.  It may be helpful to include information on what versions of LabVIEW FPGA and NI-RIO you have on your machine as well.  Let us know what you find.  Thanks!

Thaison V
Applications Engineer
National Instruments