downsampling FPGA

[flote]

Hello everybody!!

With the program attached. I have been trying to do a downsampling in the transfer loop. I want to transfer one sample and throw away 10. To ge it, I modified the transfer loop. I have only changed this and before this change everything worked good. The program compile ok but when I test it, The FPGA is reset and in the host computer i get an error.

A dpf descrbing the problem and a the program are attached join this e-mail.

Thanks and have a nice day.

[flote]

noboday knows saomething about this topic?

[Jorge_C]

Hello!

I have been looking your code, and i have found some things that may cause the problem.

I tried the code in a simulated device, and all the overflow leds in the FPGA were on. I could't find any documentation (or the subVI in the project) about the FIR_LP_Core (i have only been able to check the context help, and the maximum sampling rate its suspicious to me). If you could give me some more information about it, I think we will figure it out faster.

When simulating the FPGA VI, the filter is not able to give an output until a lot of iterations of the other loops. For example, in the last simulation, I got 215963 iterations of the first loop, and 4591 in the second.

This problem makes all the rest of the FIFOs to overflow, as you wait for the two queues to have elements available (and only one of them has them).

Also, i have seen that in the main VI, you request 8000000 samples from a queue which is much smaller (DMA - FPGA to Host).

Just in case, you can check this link out (sometimes you can get the 50400 error from hardware not working properly): http://digital.ni.com/public.nsf/allkb/95328C2FAF9DA99A862576E200785C11?OpenDocument 

I hope this was useful!

[Jorge_C]

Hello again!

I have been reviewing your code, and i just have two questions. Did it worked befire the last changes (with the host in your computer and everything)? And, could you send me a picture of the old one, or circle the new things in a picture?

You are not exactly doing what you expect, as you are getting 9 samples and throwing away one (the select case is ok, but the exit of the <? gate is true 9 out of 10 times). If you want to get 1 sample and throw away 10, change the 10 for a 11, and invert the output of the <? gate after the select, and before going out the case. I know this is not the problem, but i am just trying to help ;).

Which FPGA target do you have? I got this sentence: "However, for most common configurations, a DA FIR filter can run at 120 MHz on a Virtex II target and at 200 MHz on a Virtex 5 target.", from this link, that i guess you already know: http://zone.ni.com/devzone/cda/tut/p/id/9700. If you didn't find a problem before the downsampling modifications, this won't be the problem...

Greetings!