LabVIEW

custom FPGA test bench

There's not much documentation on creating testbenches for simulating FPGA VIs on the development computer. The tutorial walks through the basics, but it doesn't really explain the mechanisms or gotchas. For example, you can put a FOR loop in the testbench subVI, but it won't execute. It won't even give you an error, but it won't execute. I'm assuming that means that each call to the testbench corresponds to a single cycle of something.

I need to create a specific bus transaction in the testbench; it will consist of a series of pulses and edges with specific timing. I used the method from the tutorial by creating a global SimulationIndex variable and incrementing before the final case statement. So how often does LabVIEW increment this simulation index?

- at the master clock rate?

- at the SCTL clock rate?

- only when an input is read?

The third option would REALLY complicate this for me -- I'm acquiring 5 digital signals through analog inputs due to cable/connector limitations, as well as 13 digital inputs and an actual analog input. The analog input acquisitions are all running at max rate (200kHz), while the digital acquisitions are running at the SCTl clock rate (4MHz). If I need to create a 250us-wide pulse, how many SimulationIndex ticks should I wait - 50 ticks for the analog acquisition speed? 1000 ticks for the SCTL clock rate? 10,000 ticks for the master 40MHz clock? If the SimulationIndex increments only when an input is read, does that mean I can't change multiple signals at the same time?