case structure execution on a FPGA

[lmd2]

I have been programming in LV for many years but am new to FPGAs. In the following code, normally the bottom method would be the correct method; only executing the equation once instead of every iteration (100X). But I have been told that on an FPGA both cases of the case structure execute each iteration with the appropriate output being used (can someone please confirm or refute this?) if this is true there is essentially no difference?

 

 If this is true, is there any point to using a state machine on an FPGA or should all code be written 'flat'?

thanx for your help -

lmd2

[RavensFan]

Your image didn't make it into the message.  There is some problem with the path pointing to webkit-fake-url//.  You should attach your image as a file to your message.  Then you can go back and insert the image into the message based on the path to its location on NI's webserver which you can find by right clicking the attachment and selecting properties.

[lmd2]

thanx for the heads-up (although it is visible in my browser, I will attach it as a jpeg to be sure).

let me also say that in the image, I use 2 FOR loops,  which is not intended to represent the FPGA code, it is what is inside the FOR loops that I wish to optomize

thanx again

lmd2 

[Hueter · Accepted solution]

Imd2,

It is correct that on each itteration the FPGA will calculate the results of both cases. This is becasue the circuitry is being implemented in parallel hardware paths so it does not neccesarily slow down the execution. If you use the select block like in the exmaple below, this more directly shows how this will be implemented in hardware on the FPGA target.

In order to furthur optimize this code you can implment a single cycle timed loop inside of the for loop so MAX your speed.

Hunter

LabVIEW FPGA Supporter

[lmd2]

thanx for the info; there will be no FOR loop - as I stated, that was merely an illustration, the actual code will be located in a single cycle timed loop checking a byte stream, one byte per clock tick. But I need to test different indexed bytes differently and was hoping that a case structure would be better than flat code -

... bummer 😉 

thanx for verifying that a state machine will not buy me any efficiency - might as well draw flat code 

thanx again

lmd2