cRIO architecture for datalogging and control

[falseth]

Hi guys. I am developing a datalogger with some special features. The system must perform the common tasks of a datalogger and control some outputs (analogue and digital). In addition, it must also reads and writes on CAN. Due to system requirements (acquisition rates greater than 1 kHz), I can not use the Scan Mode. However, there are only three DMA channels (FIFO) to make communication with the modules. The application has the following groups of acquisition:

• input channels (digital and analog) 
• output channels (digital and analog)
• CAN (reading and writing)

After reading several articles and comments at NI site, I found that the most widely used architecture is as follows:

• high speed channels (reading) - DMA 1
• low speed channels (reading) - DMA 2
• CAN and other events (reading) - DMA 3

However, the system I'm developing does not allow this approach. So I thought of dividing the modules as follows:

* reading of slow and fast channels - DMA 1

* writing of slow and fast channels - DMA 2

* reading of CAN - DMA 3

The data written on CAN would be transferred via Front Panel Objects. I would like to receive opinions and suggestions.

My regards,

Vinicius

[ryank]

Vinicius,

Your approach seems reasonable.  One thing I would warn you about is that it can be somewhat tricky to multiplex the slow and high speed data together.  It is definitely feasible, but it just requires quite a bit of work to implement. 

You might consider doing the slow speed data with front panel objects to make your life easier.  Although you can't use the scan engine, you can use a similar architecture for synchronizing the data.  You can find out more about how the scan engine handles synchronization here: http://zone.ni.com/devzone/cda/tut/p/id/7693

Make sure to use some handshaking for the CAN messages so that you don't miss messages or send them twice.

Regards,

Ryan K.

Systems Engineer - Data Logging

National Instruments

[falseth]

Hi Ryan. Thanks for your answer. The number of slow channels will be higher than 40. Do you think I could have problems with front panel objects? One of the scenarios is composed by two CAN modules (NI 9853) and modules of other types (analog input and output, digital input and output). 

My regards,

Vinicius 

[ryank]

Assuming that most of your slow updates happen at one or two speeds, you should be able to package the data to reduce the FPGA footprint.  For example, you can pack all of your digital channels into a few U32s.  I'd suggest compiling on your intended target before locking your hardware choice in though, the CAN modules can take quite a bit of FPGA real estate.

Regards,

Ryan